1*16e939f9SJoseph Chen /* SPDX-License-Identifier: GPL-2.0 */ 2*16e939f9SJoseph Chen #ifndef __DT_BINDINGS_POWER_RK1808_POWER_H__ 3*16e939f9SJoseph Chen #define __DT_BINDINGS_POWER_RK1808_POWER_H__ 4*16e939f9SJoseph Chen 5*16e939f9SJoseph Chen /* VD_CORE */ 6*16e939f9SJoseph Chen #define RK1808_PD_A35_0 0 7*16e939f9SJoseph Chen #define RK1808_PD_A35_1 1 8*16e939f9SJoseph Chen #define RK1808_PD_SCU 2 9*16e939f9SJoseph Chen #define RK1808_VD_CORE 3 10*16e939f9SJoseph Chen 11*16e939f9SJoseph Chen /* VD_NPU */ 12*16e939f9SJoseph Chen #define RK1808_VD_NPU 4 13*16e939f9SJoseph Chen 14*16e939f9SJoseph Chen /* VD_LOGIC */ 15*16e939f9SJoseph Chen #define RK1808_PD_DDR 5 16*16e939f9SJoseph Chen #define RK1808_PD_PCIE 6 17*16e939f9SJoseph Chen #define RK1808_PD_VPU 7 18*16e939f9SJoseph Chen #define RK1808_PD_VIO 8 19*16e939f9SJoseph Chen 20*16e939f9SJoseph Chen #endif 21