1*593e1e6dSJoseph Chen /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*593e1e6dSJoseph Chen /* 3*593e1e6dSJoseph Chen * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4*593e1e6dSJoseph Chen */ 5*593e1e6dSJoseph Chen 6*593e1e6dSJoseph Chen #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H 7*593e1e6dSJoseph Chen #define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H 8*593e1e6dSJoseph Chen 9*593e1e6dSJoseph Chen #define DDR2_DS_FULL (0) 10*593e1e6dSJoseph Chen #define DDR2_DS_REDUCE (1) 11*593e1e6dSJoseph Chen 12*593e1e6dSJoseph Chen #define DDR2_ODT_DIS (0) 13*593e1e6dSJoseph Chen #define DDR2_ODT_50ohm (50) /* optional */ 14*593e1e6dSJoseph Chen #define DDR2_ODT_75ohm (75) 15*593e1e6dSJoseph Chen #define DDR2_ODT_150ohm (150) 16*593e1e6dSJoseph Chen 17*593e1e6dSJoseph Chen #define DDR3_DS_34ohm (34) 18*593e1e6dSJoseph Chen #define DDR3_DS_40ohm (40) 19*593e1e6dSJoseph Chen 20*593e1e6dSJoseph Chen #define DDR3_ODT_DIS (0) 21*593e1e6dSJoseph Chen #define DDR3_ODT_40ohm (40) 22*593e1e6dSJoseph Chen #define DDR3_ODT_60ohm (60) 23*593e1e6dSJoseph Chen #define DDR3_ODT_120ohm (120) 24*593e1e6dSJoseph Chen 25*593e1e6dSJoseph Chen #define LP2_DS_34ohm (34) 26*593e1e6dSJoseph Chen #define LP2_DS_40ohm (40) 27*593e1e6dSJoseph Chen #define LP2_DS_48ohm (48) 28*593e1e6dSJoseph Chen #define LP2_DS_60ohm (60) 29*593e1e6dSJoseph Chen #define LP2_DS_68_6ohm (68) /* optional */ 30*593e1e6dSJoseph Chen #define LP2_DS_80ohm (80) 31*593e1e6dSJoseph Chen #define LP2_DS_120ohm (120) /* optional */ 32*593e1e6dSJoseph Chen 33*593e1e6dSJoseph Chen #define LP3_DS_34ohm (34) 34*593e1e6dSJoseph Chen #define LP3_DS_40ohm (40) 35*593e1e6dSJoseph Chen #define LP3_DS_48ohm (48) 36*593e1e6dSJoseph Chen #define LP3_DS_60ohm (60) 37*593e1e6dSJoseph Chen #define LP3_DS_80ohm (80) 38*593e1e6dSJoseph Chen #define LP3_DS_34D_40U (3440) 39*593e1e6dSJoseph Chen #define LP3_DS_40D_48U (4048) 40*593e1e6dSJoseph Chen #define LP3_DS_34D_48U (3448) 41*593e1e6dSJoseph Chen 42*593e1e6dSJoseph Chen #define LP3_ODT_DIS (0) 43*593e1e6dSJoseph Chen #define LP3_ODT_60ohm (60) 44*593e1e6dSJoseph Chen #define LP3_ODT_120ohm (120) 45*593e1e6dSJoseph Chen #define LP3_ODT_240ohm (240) 46*593e1e6dSJoseph Chen 47*593e1e6dSJoseph Chen #define LP4_PDDS_40ohm (40) 48*593e1e6dSJoseph Chen #define LP4_PDDS_48ohm (48) 49*593e1e6dSJoseph Chen #define LP4_PDDS_60ohm (60) 50*593e1e6dSJoseph Chen #define LP4_PDDS_80ohm (80) 51*593e1e6dSJoseph Chen #define LP4_PDDS_120ohm (120) 52*593e1e6dSJoseph Chen #define LP4_PDDS_240ohm (240) 53*593e1e6dSJoseph Chen 54*593e1e6dSJoseph Chen #define LP4_DQ_ODT_40ohm (40) 55*593e1e6dSJoseph Chen #define LP4_DQ_ODT_48ohm (48) 56*593e1e6dSJoseph Chen #define LP4_DQ_ODT_60ohm (60) 57*593e1e6dSJoseph Chen #define LP4_DQ_ODT_80ohm (80) 58*593e1e6dSJoseph Chen #define LP4_DQ_ODT_120ohm (120) 59*593e1e6dSJoseph Chen #define LP4_DQ_ODT_240ohm (240) 60*593e1e6dSJoseph Chen #define LP4_DQ_ODT_DIS (0) 61*593e1e6dSJoseph Chen 62*593e1e6dSJoseph Chen #define LP4_CA_ODT_40ohm (40) 63*593e1e6dSJoseph Chen #define LP4_CA_ODT_48ohm (48) 64*593e1e6dSJoseph Chen #define LP4_CA_ODT_60ohm (60) 65*593e1e6dSJoseph Chen #define LP4_CA_ODT_80ohm (80) 66*593e1e6dSJoseph Chen #define LP4_CA_ODT_120ohm (120) 67*593e1e6dSJoseph Chen #define LP4_CA_ODT_240ohm (240) 68*593e1e6dSJoseph Chen #define LP4_CA_ODT_DIS (0) 69*593e1e6dSJoseph Chen 70*593e1e6dSJoseph Chen #define DDR4_DS_34ohm (34) 71*593e1e6dSJoseph Chen #define DDR4_DS_48ohm (48) 72*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_DIS (0) 73*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_60ohm (60) 74*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_120ohm (120) 75*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_40ohm (40) 76*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_240ohm (240) 77*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_48ohm (48) 78*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_80ohm (80) 79*593e1e6dSJoseph Chen #define DDR4_RTT_NOM_34ohm (34) 80*593e1e6dSJoseph Chen 81*593e1e6dSJoseph Chen #define PHY_DDR3_RON_DISABLE (0) 82*593e1e6dSJoseph Chen #define PHY_DDR3_RON_506ohm (1) 83*593e1e6dSJoseph Chen #define PHY_DDR3_RON_253ohm (2) 84*593e1e6dSJoseph Chen #define PHY_DDR3_RON_169hm (3) 85*593e1e6dSJoseph Chen #define PHY_DDR3_RON_127ohm (4) 86*593e1e6dSJoseph Chen #define PHY_DDR3_RON_101ohm (5) 87*593e1e6dSJoseph Chen #define PHY_DDR3_RON_84ohm (6) 88*593e1e6dSJoseph Chen #define PHY_DDR3_RON_72ohm (7) 89*593e1e6dSJoseph Chen #define PHY_DDR3_RON_63ohm (16) 90*593e1e6dSJoseph Chen #define PHY_DDR3_RON_56ohm (17) 91*593e1e6dSJoseph Chen #define PHY_DDR3_RON_51ohm (18) 92*593e1e6dSJoseph Chen #define PHY_DDR3_RON_46ohm (19) 93*593e1e6dSJoseph Chen #define PHY_DDR3_RON_42ohm (20) 94*593e1e6dSJoseph Chen #define PHY_DDR3_RON_39ohm (21) 95*593e1e6dSJoseph Chen #define PHY_DDR3_RON_36ohm (22) 96*593e1e6dSJoseph Chen #define PHY_DDR3_RON_34ohm (23) 97*593e1e6dSJoseph Chen #define PHY_DDR3_RON_32ohm (24) 98*593e1e6dSJoseph Chen #define PHY_DDR3_RON_30ohm (25) 99*593e1e6dSJoseph Chen #define PHY_DDR3_RON_28ohm (26) 100*593e1e6dSJoseph Chen #define PHY_DDR3_RON_27ohm (27) 101*593e1e6dSJoseph Chen #define PHY_DDR3_RON_25ohm (28) 102*593e1e6dSJoseph Chen #define PHY_DDR3_RON_24ohm (29) 103*593e1e6dSJoseph Chen #define PHY_DDR3_RON_23ohm (30) 104*593e1e6dSJoseph Chen #define PHY_DDR3_RON_22ohm (31) 105*593e1e6dSJoseph Chen 106*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_DISABLE (0) 107*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_953ohm (1) 108*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_483ohm (2) 109*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_320ohm (3) 110*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_241ohm (4) 111*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_193ohm (5) 112*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_161ohm (6) 113*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_138ohm (7) 114*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_121ohm (16) 115*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_107ohm (17) 116*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_97ohm (18) 117*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_88ohm (19) 118*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_80ohm (20) 119*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_74ohm (21) 120*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_69ohm (22) 121*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_64ohm (23) 122*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_60ohm (24) 123*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_57ohm (25) 124*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_54ohm (26) 125*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_51ohm (27) 126*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_48ohm (28) 127*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_46ohm (29) 128*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_44ohm (30) 129*593e1e6dSJoseph Chen #define PHY_DDR3_RTT_42ohm (31) 130*593e1e6dSJoseph Chen 131*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_DISABLE (0) 132*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_570ohm (1) 133*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_285ohm (2) 134*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_190ohm (3) 135*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_142ohm (4) 136*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_114ohm (5) 137*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_95ohm (6) 138*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_81ohm (7) 139*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_71ohm (16) 140*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_63ohm (17) 141*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_57ohm (18) 142*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_52ohm (19) 143*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_47ohm (20) 144*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_44ohm (21) 145*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_41ohm (22) 146*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_38ohm (23) 147*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_36ohm (24) 148*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_34ohm (25) 149*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_32ohm (26) 150*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_30ohm (27) 151*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_28ohm (28) 152*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_27ohm (29) 153*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_26ohm (30) 154*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RON_25ohm (31) 155*593e1e6dSJoseph Chen 156*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_DISABLE (0) 157*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_973ohm (1) 158*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_493ohm (2) 159*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_327ohm (3) 160*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_247ohm (4) 161*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_197ohm (5) 162*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_164ohm (6) 163*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_141ohm (7) 164*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_123ohm (16) 165*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_109ohm (17) 166*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_99ohm (18) 167*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_90ohm (19) 168*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_82ohm (20) 169*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_76ohm (21) 170*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_70ohm (22) 171*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_66ohm (23) 172*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_62ohm (24) 173*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_58ohm (25) 174*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_55ohm (26) 175*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_52ohm (27) 176*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_49ohm (28) 177*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_47ohm (29) 178*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_45ohm (30) 179*593e1e6dSJoseph Chen #define PHY_DDR4_LPDDR3_RTT_43ohm (31) 180*593e1e6dSJoseph Chen 181*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_DISABLE (0) 182*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_606ohm (1) 183*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_303ohm (2) 184*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_202ohm (3) 185*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_152ohm (4) 186*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_121ohm (5) 187*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_101ohm (6) 188*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_87ohm (7) 189*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_76ohm (16) 190*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_67ohm (17) 191*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_61ohm (18) 192*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_55ohm (19) 193*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_51ohm (20) 194*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_47ohm (21) 195*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_43ohm (22) 196*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_40ohm (23) 197*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_38ohm (24) 198*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_36ohm (25) 199*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_34ohm (26) 200*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_32ohm (27) 201*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_30ohm (28) 202*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_29ohm (29) 203*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_28ohm (30) 204*593e1e6dSJoseph Chen #define PHY_LPDDR4_RON_26ohm (31) 205*593e1e6dSJoseph Chen 206*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_DISABLE (0) 207*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_998ohm (1) 208*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_506ohm (2) 209*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_336ohm (3) 210*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_253ohm (4) 211*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_202ohm (5) 212*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_169ohm (6) 213*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_144ohm (7) 214*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_127ohm (16) 215*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_112ohm (17) 216*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_101ohm (18) 217*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_92ohm (19) 218*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_84ohm (20) 219*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_78ohm (21) 220*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_72ohm (22) 221*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_67ohm (23) 222*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_63ohm (24) 223*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_60ohm (25) 224*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_56ohm (26) 225*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_53ohm (27) 226*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_51ohm (28) 227*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_48ohm (29) 228*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_46ohm (30) 229*593e1e6dSJoseph Chen #define PHY_LPDDR4_RTT_44ohm (31) 230*593e1e6dSJoseph Chen 231*593e1e6dSJoseph Chen #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/ 232