1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ROCKCHIP_MIPI_DSI_H__ 8 #define __ROCKCHIP_MIPI_DSI_H__ 9 10 /* request ACK from peripheral */ 11 #define MIPI_DSI_MSG_REQ_ACK BIT(0) 12 /* use Low Power Mode to transmit message */ 13 #define MIPI_DSI_MSG_USE_LPM BIT(1) 14 15 /* DSI mode flags */ 16 17 /* video mode */ 18 #define MIPI_DSI_MODE_VIDEO BIT(0) 19 /* video burst mode */ 20 #define MIPI_DSI_MODE_VIDEO_BURST BIT(1) 21 /* video pulse mode */ 22 #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) 23 /* enable auto vertical count mode */ 24 #define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) 25 /* enable hsync-end packets in vsync-pulse and v-porch area */ 26 #define MIPI_DSI_MODE_VIDEO_HSE BIT(4) 27 /* disable hfront-porch area */ 28 #define MIPI_DSI_MODE_VIDEO_HFP BIT(5) 29 /* disable hback-porch area */ 30 #define MIPI_DSI_MODE_VIDEO_HBP BIT(6) 31 /* disable hsync-active area */ 32 #define MIPI_DSI_MODE_VIDEO_HSA BIT(7) 33 /* flush display FIFO on vsync pulse */ 34 #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) 35 /* disable EoT packets in HS mode */ 36 #define MIPI_DSI_MODE_EOT_PACKET BIT(9) 37 /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ 38 #define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) 39 /* transmit data in low power */ 40 #define MIPI_DSI_MODE_LPM BIT(11) 41 42 #define MIPI_DSI_DCS_POWER_MODE_DISPLAY (1 << 2) 43 #define MIPI_DSI_DCS_POWER_MODE_NORMAL (1 << 3) 44 #define MIPI_DSI_DCS_POWER_MODE_SLEEP (1 << 4) 45 #define MIPI_DSI_DCS_POWER_MODE_PARTIAL (1 << 5) 46 #define MIPI_DSI_DCS_POWER_MODE_IDLE (1 << 6) 47 48 #endif /* __ROCKCHIP_MIPI_DSI__ */ 49