13335786aSStefan Roese /* 23335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 33335786aSStefan Roese * 43335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 53335786aSStefan Roese */ 63335786aSStefan Roese 73335786aSStefan Roese #ifndef _COMPHY_DATA_H_ 83335786aSStefan Roese #define _COMPHY_DATA_H_ 93335786aSStefan Roese 103335786aSStefan Roese #define PHY_SPEED_1_25G 0 113335786aSStefan Roese #define PHY_SPEED_1_5G 1 123335786aSStefan Roese #define PHY_SPEED_2_5G 2 133335786aSStefan Roese #define PHY_SPEED_3G 3 143335786aSStefan Roese #define PHY_SPEED_3_125G 4 153335786aSStefan Roese #define PHY_SPEED_5G 5 163335786aSStefan Roese #define PHY_SPEED_6G 6 173335786aSStefan Roese #define PHY_SPEED_6_25G 7 183335786aSStefan Roese #define PHY_SPEED_10_3125G 8 193335786aSStefan Roese #define PHY_SPEED_MAX 9 203335786aSStefan Roese #define PHY_SPEED_INVALID 0xff 213335786aSStefan Roese 223335786aSStefan Roese #define PHY_TYPE_UNCONNECTED 0 233335786aSStefan Roese #define PHY_TYPE_PEX0 1 243335786aSStefan Roese #define PHY_TYPE_PEX1 2 253335786aSStefan Roese #define PHY_TYPE_PEX2 3 263335786aSStefan Roese #define PHY_TYPE_PEX3 4 273335786aSStefan Roese #define PHY_TYPE_SATA0 5 283335786aSStefan Roese #define PHY_TYPE_SATA1 6 293335786aSStefan Roese #define PHY_TYPE_SATA2 7 303335786aSStefan Roese #define PHY_TYPE_SATA3 8 313335786aSStefan Roese #define PHY_TYPE_SGMII0 9 323335786aSStefan Roese #define PHY_TYPE_SGMII1 10 333335786aSStefan Roese #define PHY_TYPE_SGMII2 11 343335786aSStefan Roese #define PHY_TYPE_SGMII3 12 353335786aSStefan Roese #define PHY_TYPE_QSGMII 13 363335786aSStefan Roese #define PHY_TYPE_USB3_HOST0 14 373335786aSStefan Roese #define PHY_TYPE_USB3_HOST1 15 383335786aSStefan Roese #define PHY_TYPE_USB3_DEVICE 16 393335786aSStefan Roese #define PHY_TYPE_XAUI0 17 403335786aSStefan Roese #define PHY_TYPE_XAUI1 18 413335786aSStefan Roese #define PHY_TYPE_XAUI2 19 423335786aSStefan Roese #define PHY_TYPE_XAUI3 20 433335786aSStefan Roese #define PHY_TYPE_RXAUI0 21 443335786aSStefan Roese #define PHY_TYPE_RXAUI1 22 45cb686454SStefan Roese #define PHY_TYPE_SFI 23 463335786aSStefan Roese #define PHY_TYPE_MAX 24 473335786aSStefan Roese #define PHY_TYPE_INVALID 0xff 483335786aSStefan Roese 493335786aSStefan Roese #define PHY_POLARITY_NO_INVERT 0 503335786aSStefan Roese #define PHY_POLARITY_TXD_INVERT 1 513335786aSStefan Roese #define PHY_POLARITY_RXD_INVERT 2 523335786aSStefan Roese #define PHY_POLARITY_ALL_INVERT \ 533335786aSStefan Roese (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) 543335786aSStefan Roese 55*e89acc4bSStefan Roese #define UTMI_PHY_TO_USB3_HOST0 0 56*e89acc4bSStefan Roese #define UTMI_PHY_TO_USB3_HOST1 1 57*e89acc4bSStefan Roese #define UTMI_PHY_TO_USB3_DEVICE0 2 583335786aSStefan Roese #define UTMI_PHY_INVALID 0xff 593335786aSStefan Roese 603335786aSStefan Roese #endif /* _COMPHY_DATA_H_ */ 613335786aSStefan Roese 62