1*3335786aSStefan Roese /* 2*3335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 3*3335786aSStefan Roese * 4*3335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*3335786aSStefan Roese */ 6*3335786aSStefan Roese 7*3335786aSStefan Roese #ifndef _COMPHY_DATA_H_ 8*3335786aSStefan Roese #define _COMPHY_DATA_H_ 9*3335786aSStefan Roese 10*3335786aSStefan Roese #define PHY_SPEED_1_25G 0 11*3335786aSStefan Roese #define PHY_SPEED_1_5G 1 12*3335786aSStefan Roese #define PHY_SPEED_2_5G 2 13*3335786aSStefan Roese #define PHY_SPEED_3G 3 14*3335786aSStefan Roese #define PHY_SPEED_3_125G 4 15*3335786aSStefan Roese #define PHY_SPEED_5G 5 16*3335786aSStefan Roese #define PHY_SPEED_6G 6 17*3335786aSStefan Roese #define PHY_SPEED_6_25G 7 18*3335786aSStefan Roese #define PHY_SPEED_10_3125G 8 19*3335786aSStefan Roese #define PHY_SPEED_MAX 9 20*3335786aSStefan Roese #define PHY_SPEED_INVALID 0xff 21*3335786aSStefan Roese 22*3335786aSStefan Roese #define PHY_TYPE_UNCONNECTED 0 23*3335786aSStefan Roese #define PHY_TYPE_PEX0 1 24*3335786aSStefan Roese #define PHY_TYPE_PEX1 2 25*3335786aSStefan Roese #define PHY_TYPE_PEX2 3 26*3335786aSStefan Roese #define PHY_TYPE_PEX3 4 27*3335786aSStefan Roese #define PHY_TYPE_SATA0 5 28*3335786aSStefan Roese #define PHY_TYPE_SATA1 6 29*3335786aSStefan Roese #define PHY_TYPE_SATA2 7 30*3335786aSStefan Roese #define PHY_TYPE_SATA3 8 31*3335786aSStefan Roese #define PHY_TYPE_SGMII0 9 32*3335786aSStefan Roese #define PHY_TYPE_SGMII1 10 33*3335786aSStefan Roese #define PHY_TYPE_SGMII2 11 34*3335786aSStefan Roese #define PHY_TYPE_SGMII3 12 35*3335786aSStefan Roese #define PHY_TYPE_QSGMII 13 36*3335786aSStefan Roese #define PHY_TYPE_USB3_HOST0 14 37*3335786aSStefan Roese #define PHY_TYPE_USB3_HOST1 15 38*3335786aSStefan Roese #define PHY_TYPE_USB3_DEVICE 16 39*3335786aSStefan Roese #define PHY_TYPE_XAUI0 17 40*3335786aSStefan Roese #define PHY_TYPE_XAUI1 18 41*3335786aSStefan Roese #define PHY_TYPE_XAUI2 19 42*3335786aSStefan Roese #define PHY_TYPE_XAUI3 20 43*3335786aSStefan Roese #define PHY_TYPE_RXAUI0 21 44*3335786aSStefan Roese #define PHY_TYPE_RXAUI1 22 45*3335786aSStefan Roese #define PHY_TYPE_KR 23 46*3335786aSStefan Roese #define PHY_TYPE_MAX 24 47*3335786aSStefan Roese #define PHY_TYPE_INVALID 0xff 48*3335786aSStefan Roese 49*3335786aSStefan Roese #define PHY_POLARITY_NO_INVERT 0 50*3335786aSStefan Roese #define PHY_POLARITY_TXD_INVERT 1 51*3335786aSStefan Roese #define PHY_POLARITY_RXD_INVERT 2 52*3335786aSStefan Roese #define PHY_POLARITY_ALL_INVERT \ 53*3335786aSStefan Roese (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) 54*3335786aSStefan Roese 55*3335786aSStefan Roese #define UTMI_PHY_TO_USB_HOST0 0 56*3335786aSStefan Roese #define UTMI_PHY_TO_USB_HOST1 1 57*3335786aSStefan Roese #define UTMI_PHY_TO_USB_DEVICE0 2 58*3335786aSStefan Roese #define UTMI_PHY_INVALID 0xff 59*3335786aSStefan Roese 60*3335786aSStefan Roese #endif /* _COMPHY_DATA_H_ */ 61*3335786aSStefan Roese 62