1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H 9 10 /* pll clocks */ 11 #define PLL_GPLL 1 12 #define ARMCLK 2 13 14 /* clk (clocks) */ 15 #define XIN_OSC0_HALF 5 16 #define CLK_GPLL_DIV24 6 17 #define CLK_GPLL_DIV12 7 18 #define CLK_GPLL_DIV6 8 19 #define CLK_GPLL_DIV4 9 20 #define CLK_GPLL_DIV3 10 21 #define CLK_GPLL_DIV2P5 11 22 #define CLK_GPLL_DIV2 12 23 #define CLK_UART0_SRC 13 24 #define CLK_UART1_SRC 14 25 #define CLK_UART2_SRC 15 26 #define CLK_UART0_FRAC 16 27 #define CLK_UART1_FRAC 17 28 #define CLK_UART2_FRAC 18 29 #define CLK_SAI_SRC 19 30 #define CLK_SAI_FRAC 20 31 #define LSCLK_NPU_SRC 21 32 #define CLK_NPU_SRC 22 33 #define ACLK_VEPU_SRC 23 34 #define CLK_VEPU_SRC 24 35 #define ACLK_VI_SRC 25 36 #define CLK_ISP_SRC 26 37 #define DCLK_VICAP 27 38 #define CCLK_EMMC 28 39 #define CCLK_SDMMC0 29 40 #define SCLK_SFC_2X 30 41 #define LSCLK_PERI_SRC 31 42 #define ACLK_PERI_SRC 32 43 #define HCLK_HPMCU 33 44 #define SCLK_UART0 34 45 #define SCLK_UART1 35 46 #define SCLK_UART2 36 47 #define CLK_I2C_PMU 37 48 #define CLK_I2C_PERI 38 49 #define CLK_SPI0 39 50 #define CLK_PWM0_SRC 40 51 #define CLK_PWM1 41 52 #define CLK_PWM2 42 53 #define DCLK_DECOM_SRC 43 54 #define CCLK_SDMMC1 44 55 #define CLK_CORE_CRYPTO 45 56 #define CLK_PKA_CRYPTO 46 57 #define CLK_CORE_RGA 47 58 #define MCLK_SAI_SRC 48 59 #define CLK_FREQ_PWM0_SRC 49 60 #define CLK_COUNTER_PWM0_SRC 50 61 #define PCLK_TOP_ROOT 51 62 #define CLK_REF_MIPI0 52 63 #define CLK_MIPI0_OUT2IO 53 64 #define CLK_REF_MIPI1 54 65 #define CLK_MIPI1_OUT2IO 55 66 #define MCLK_SAI_OUT2IO 56 67 #define ACLK_NPU_ROOT 57 68 #define HCLK_RKNN 58 69 #define ACLK_RKNN 59 70 #define LSCLK_VEPU_ROOT 60 71 #define HCLK_VEPU 61 72 #define ACLK_VEPU 62 73 #define CLK_CORE_VEPU 63 74 #define PCLK_IOC_VCCIO3 64 75 #define PCLK_ACODEC 65 76 #define PCLK_USBPHY 66 77 #define LSCLK_VI_100M 67 78 #define LSCLK_VI_ROOT 68 79 #define HCLK_ISP 69 80 #define ACLK_ISP 70 81 #define CLK_CORE_ISP 71 82 #define ACLK_VICAP 72 83 #define HCLK_VICAP 73 84 #define ISP0CLK_VICAP 74 85 #define PCLK_CSI2HOST0 75 86 #define PCLK_CSI2HOST1 76 87 #define HCLK_EMMC 77 88 #define HCLK_SFC 78 89 #define HCLK_SFC_XIP 79 90 #define HCLK_SDMMC0 80 91 #define PCLK_CSIPHY 81 92 #define PCLK_GPIO1 82 93 #define DBCLK_GPIO1 83 94 #define PCLK_IOC_VCCIO47 84 95 #define LSCLK_DDR_ROOT 85 96 #define CLK_TIMER_DDRMON 86 97 #define LSCLK_PMU_ROOT 87 98 #define PCLK_PMU 88 99 #define XIN_RC_DIV 89 100 #define CLK_32K 90 101 #define PCLK_PMU_GPIO0 91 102 #define DBCLK_PMU_GPIO0 92 103 #define CLK_DDR_FAIL_SAFE 93 104 #define PCLK_PMU_HP_TIMER 94 105 #define CLK_PMU_32K_HP_TIMER 95 106 #define PCLK_PWM0 96 107 #define CLK_PWM0 97 108 #define CLK_OSC_PWM0 98 109 #define CLK_RC_PWM0 99 110 #define CLK_FREQ_PWM0 100 111 #define CLK_COUNTER_PWM0 101 112 #define PCLK_I2C0 102 113 #define CLK_I2C0 103 114 #define PCLK_UART0 104 115 #define PCLK_IOC_PMUIO0 105 116 #define CLK_REFOUT 106 117 #define CLK_PREROLL 107 118 #define CLK_PREROLL_32K 108 119 #define CLK_LPMCU_PMU 109 120 #define PCLK_SPI2AHB 110 121 #define HCLK_SPI2AHB 111 122 #define SCLK_SPI2AHB 112 123 #define PCLK_WDT_LPMCU 113 124 #define TCLK_WDT_LPMCU 114 125 #define HCLK_SFC_PMU1 115 126 #define HCLK_SFC_XIP_PMU1 116 127 #define SCLK_SFC_2X_PMU1 117 128 #define CLK_LPMCU 118 129 #define CLK_LPMCU_RTC 119 130 #define PCLK_LPMCU_MAILBOX 120 131 #define PCLK_IOC_PMUIO1 121 132 #define PCLK_CRU_PMU1 122 133 #define PCLK_PERI_ROOT 123 134 #define PCLK_RTC_ROOT 124 135 #define CLK_TIMER_ROOT 125 136 #define PCLK_TIMER 126 137 #define CLK_TIMER0 127 138 #define CLK_TIMER1 128 139 #define CLK_TIMER2 129 140 #define CLK_TIMER3 130 141 #define CLK_TIMER4 131 142 #define CLK_TIMER5 132 143 #define PCLK_STIMER 133 144 #define CLK_STIMER0 134 145 #define CLK_STIMER1 135 146 #define PCLK_WDT_NS 136 147 #define TCLK_WDT_NS 137 148 #define PCLK_WDT_S 138 149 #define TCLK_WDT_S 139 150 #define PCLK_WDT_HPMCU 140 151 #define TCLK_WDT_HPMCU 141 152 #define PCLK_I2C1 142 153 #define CLK_I2C1 143 154 #define PCLK_I2C2 144 155 #define CLK_I2C2 145 156 #define PCLK_I2C3 146 157 #define CLK_I2C3 147 158 #define PCLK_I2C4 148 159 #define CLK_I2C4 149 160 #define PCLK_SPI0 150 161 #define PCLK_PWM1 151 162 #define CLK_OSC_PWM1 152 163 #define PCLK_PWM2 153 164 #define CLK_OSC_PWM2 154 165 #define PCLK_UART2 155 166 #define PCLK_UART1 156 167 #define ACLK_RKDMA 157 168 #define PCLK_TSADC 158 169 #define CLK_TSADC 159 170 #define CLK_TSADC_TSEN 160 171 #define PCLK_SARADC 161 172 #define CLK_SARADC 162 173 #define PCLK_GPIO2 163 174 #define DBCLK_GPIO2 164 175 #define PCLK_IOC_VCCIO6 165 176 #define ACLK_USBOTG 166 177 #define CLK_REF_USBOTG 167 178 #define HCLK_SDMMC1 168 179 #define HCLK_SAI 169 180 #define MCLK_SAI 170 181 #define ACLK_CRYPTO 171 182 #define HCLK_CRYPTO 172 183 #define HCLK_RK_RNG_NS 173 184 #define HCLK_RK_RNG_S 174 185 #define PCLK_OTPC_NS 175 186 #define CLK_OTPC_ROOT_NS 176 187 #define CLK_SBPI_OTPC_NS 177 188 #define CLK_USER_OTPC_NS 178 189 #define PCLK_OTPC_S 179 190 #define CLK_OTPC_ROOT_S 180 191 #define CLK_SBPI_OTPC_S 181 192 #define CLK_USER_OTPC_S 182 193 #define CLK_OTPC_ARB 183 194 #define PCLK_OTP_MASK 184 195 #define HCLK_RGA 185 196 #define ACLK_RGA 186 197 #define ACLK_MAC 187 198 #define PCLK_MAC 188 199 #define CLK_MACPHY 189 200 #define ACLK_SPINLOCK 190 201 #define HCLK_CACHE 191 202 #define PCLK_HPMCU_MAILBOX 192 203 #define PCLK_HPMCU_INTMUX 193 204 #define CLK_HPMCU 194 205 #define CLK_HPMCU_RTC 195 206 #define DCLK_DECOM 196 207 #define ACLK_DECOM 197 208 #define PCLK_DECOM 198 209 #define ACLK_SYS_SRAM 199 210 #define PCLK_DMA2DDR 200 211 #define ACLK_DMA2DDR 201 212 #define PCLK_DCF 202 213 #define ACLK_DCF 203 214 #define MCLK_ACODEC_TX 204 215 #define SCLK_UART0_SRC 205 216 #define SCLK_UART1_SRC 206 217 #define SCLK_UART2_SRC 207 218 #define XIN_RC_SRC 208 219 #define CLK_UTMI_USBOTG 209 220 #define CLK_REF_USBPHY 230 221 222 #define CLK_NR_CLKS (CLK_REF_USBPHY + 1) 223 224 // PERICRU_SOFTRST_CON00(Offset:0xA00) 225 #define SRST_ARESETN_PERI_BIU 0x00000002 226 #define SRST_HRESETN_HPMCU_BIU 0x00000003 227 #define SRST_LSRESETN_PERI_BIU 0x00000004 228 #define SRST_PRESETN_PERI_BIU 0x00000005 229 #define SRST_PRESETN_RTC_BIU 0x00000006 230 #define SRST_HRESETN_BOOTROM 0x00000007 231 232 // PERICRU_SOFTRST_CON01(Offset:0xA04) 233 #define SRST_PRESETN_TIMER 0x00000010 234 #define SRST_RESETN_TIMER0 0x00000011 235 #define SRST_RESETN_TIMER1 0x00000012 236 #define SRST_RESETN_TIMER2 0x00000013 237 #define SRST_RESETN_TIMER3 0x00000014 238 #define SRST_RESETN_TIMER4 0x00000015 239 #define SRST_RESETN_TIMER5 0x00000016 240 #define SRST_PRESETN_STIMER 0x00000017 241 #define SRST_RESETN_STIMER0 0x00000018 242 #define SRST_RESETN_STIMER1 0x00000019 243 244 // PERICRU_SOFTRST_CON02(Offset:0xA08) 245 #define SRST_PRESETN_WDT_NS 0x00000020 246 #define SRST_TRESETN_WDT_NS 0x00000021 247 #define SRST_PRESETN_WDT_S 0x00000022 248 #define SRST_TRESETN_WDT_S 0x00000023 249 #define SRST_PRESETN_WDT_HPMCU 0x00000024 250 #define SRST_TRESETN_WDT_HPMCU 0x00000025 251 #define SRST_PRESETN_I2C1 0x00000026 252 #define SRST_RESETN_I2C1 0x00000027 253 #define SRST_PRESETN_I2C2 0x00000028 254 #define SRST_RESETN_I2C2 0x00000029 255 #define SRST_PRESETN_I2C3 0x0000002A 256 #define SRST_RESETN_I2C3 0x0000002B 257 #define SRST_PRESETN_I2C4 0x0000002C 258 #define SRST_RESETN_I2C4 0x0000002D 259 260 // PERICRU_SOFTRST_CON03(Offset:0xA0C) 261 #define SRST_PRESETN_UART2 0x00000030 262 #define SRST_SRESETN_UART2 0x00000031 263 #define SRST_PRESETN_UART1 0x00000032 264 #define SRST_SRESETN_UART1 0x00000033 265 #define SRST_PRESETN_SPI0 0x0000003A 266 #define SRST_RESETN_SPI0 0x0000003B 267 268 // PERICRU_SOFTRST_CON04(Offset:0xA10) 269 #define SRST_PRESETN_PWM1 0x00000046 270 #define SRST_RESETN_PWM1 0x00000047 271 #define SRST_PRESETN_PWM2 0x0000004C 272 #define SRST_RESETN_PWM2 0x0000004D 273 274 // PERICRU_SOFTRST_CON05(Offset:0xA14) 275 #define SRST_ARESETN_RKDMA 0x00000058 276 #define SRST_PRESETN_TSADC 0x00000059 277 #define SRST_RESETN_TSADC 0x0000005A 278 #define SRST_PRESETN_SARADC 0x0000005C 279 #define SRST_RESETN_SARADC 0x0000005D 280 281 // PERICRU_SOFTRST_CON06(Offset:0xA18) 282 #define SRST_RESETN_SARADC_PHY 0x00000060 283 #define SRST_PRESETN_RTC_TEST 0x00000061 284 #define SRST_PRESETN_GPIO2 0x00000063 285 #define SRST_DBRESETN_GPIO2 0x00000064 286 #define SRST_PRESETN_IOC_VCCIO6 0x00000065 287 #define SRST_PRESETN_PERI_SGRF 0x00000066 288 #define SRST_PRESETN_PERI_GRF 0x00000067 289 #define SRST_PRESETN_CRU_PERI 0x00000068 290 #define SRST_ARESETN_USBOTG 0x00000069 291 292 // PERICRU_SOFTRST_CON07(Offset:0xA1C) 293 #define SRST_HRESETN_SDMMC1 0x00000070 294 #define SRST_HRESETN_SAI 0x00000071 295 #define SRST_MRESETN_SAI 0x00000072 296 297 // PERICRU_SOFTRST_CON08(Offset:0xA20) 298 #define SRST_RESETN_CORE_CRYPTO 0x00000080 299 #define SRST_RESETN_PKA_CRYPTO 0x00000081 300 #define SRST_ARESETN_CRYPTO 0x00000082 301 #define SRST_HRESETN_CRYPTO 0x00000083 302 #define SRST_HRESETN_RK_RNG_NS 0x00000084 303 #define SRST_HRESETN_RK_RNG_S 0x00000085 304 #define SRST_PRESETN_OTPC_NS 0x00000086 305 #define SRST_RESETN_SBPI_OTPC_NS 0x00000088 306 #define SRST_RESETN_USER_OTPC_NS 0x00000089 307 #define SRST_PRESETN_OTPC_S 0x0000008A 308 #define SRST_RESETN_SBPI_OTPC_S 0x0000008C 309 #define SRST_RESETN_USER_OTPC_S 0x0000008D 310 #define SRST_RESETN_OTPC_ARB 0x0000008E 311 #define SRST_PRESETN_OTP_MASK 0x0000008F 312 313 // PERICRU_SOFTRST_CON09(Offset:0xA24) 314 #define SRST_HRESETN_RGA 0x00000090 315 #define SRST_ARESETN_RGA 0x00000091 316 #define SRST_RESETN_CORE_RGA 0x00000092 317 #define SRST_ARESETN_MAC 0x00000093 318 #define SRST_RESETN_MACPHY 0x0000009B 319 320 // PERICRU_SOFTRST_CON10(Offset:0xA28) 321 #define SRST_ARESETN_SPINLOCK 0x000000A0 322 #define SRST_HRESETN_CACHE 0x000000A1 323 #define SRST_PRESETN_HPMCU_MAILBOX 0x000000A2 324 #define SRST_PRESETN_HPMCU_INTMUX 0x000000A3 325 #define SRST_RESETN_HPMCU_FULL_CLUSTER 0x000000A4 326 #define SRST_RESETN_HPMCU_PWUP 0x000000A5 327 #define SRST_RESETN_HPMCU_ONLY_CORE 0x000000A6 328 #define SRST_TRESETN_HPMCU_JTAG 0x000000A7 329 330 // PERICRU_SOFTRST_CON11(Offset:0xA2C) 331 #define SRST_DRESETN_DECOM 0x000000B0 332 #define SRST_ARESETN_DECOM 0x000000B1 333 #define SRST_PRESETN_DECOM 0x000000B2 334 #define SRST_ARESETN_SYS_SRAM 0x000000B3 335 #define SRST_PRESETN_DMA2DDR 0x000000B4 336 #define SRST_ARESETN_DMA2DDR 0x000000B5 337 #define SRST_PRESETN_DCF 0x000000B6 338 #define SRST_ARESETN_DCF 0x000000B7 339 #define SRST_RESETN_USBPHY_POR 0x000000BC 340 #define SRST_RESETN_USBPHY_OTG 0x000000BD 341 342 // ======================= VEPUCRU module definition bank=1 ======================= 343 // VEPUCRU_SOFTRST_CON00(Offset:0xA00) 344 #define SRST_ARESETN_VEPU_BIU 0x00040001 345 #define SRST_LSRESETN_VEPU_BIU 0x00040002 346 #define SRST_RESETN_REF_PVTPLL_VEPU 0x00040003 347 #define SRST_HRESETN_VEPU 0x00040004 348 #define SRST_ARESETN_VEPU 0x00040005 349 #define SRST_RESETN_CORE_VEPU 0x00040006 350 #define SRST_PRESETN_VEPU_PVTPLL 0x00040007 351 #define SRST_PRESETN_CRU_VEPU 0x00040008 352 #define SRST_PRESETN_VEPU_GRF 0x0004000A 353 #define SRST_PRESETN_IOC_VCCIO3 0x0004000B 354 #define SRST_PRESETN_ACODEC 0x0004000D 355 #define SRST_PRESETN_USBPHY 0x0004000E 356 357 // ======================= NPUCRU module definition bank=2 ======================== 358 // NPUCRU_SOFTRST_CON00(Offset:0xA00) 359 #define SRST_RESETN_REF_PVTPLL_NPU 0x00080000 360 #define SRST_ARESETN_NPU_BIU 0x00080002 361 #define SRST_LSRESETN_NPU_BIU 0x00080003 362 #define SRST_HRESETN_RKNN 0x00080004 363 #define SRST_ARESETN_RKNN 0x00080005 364 #define SRST_PRESETN_NPU_PVTPLL 0x00080006 365 #define SRST_PRESETN_CRU_NPU 0x00080007 366 #define SRST_PRESETN_NPU_GRF 0x00080009 367 368 // ======================== VICRU module definition bank=3 ======================== 369 // VICRU_SOFTRST_CON00(Offset:0xA00) 370 #define SRST_LSRESETN_VI_BIU 0x000c0001 371 #define SRST_ARESETN_VI_BIU 0x000c0002 372 #define SRST_RESETN_REF_PVTPLL_ISP 0x000c0003 373 #define SRST_RESETN_CORE_ISP 0x000c0006 374 375 // VICRU_SOFTRST_CON01(Offset:0xA04) 376 #define SRST_DRESETN_VICAP 0x000c0010 377 #define SRST_ARESETN_VICAP 0x000c0012 378 #define SRST_HRESETN_VICAP 0x000c0013 379 #define SRST_ISP0RESETN_VICAP 0x000c0018 380 #define SRST_PRESETN_CSI2HOST0 0x000c0019 381 #define SRST_PRESETN_CSI2HOST1 0x000c001B 382 #define SRST_SRESETN_SFC_2X 0x000c001C 383 #define SRST_HRESETN_EMMC 0x000c001D 384 #define SRST_HRESETN_SFC 0x000c001E 385 #define SRST_HRESETN_SFC_XIP 0x000c001F 386 387 // VICRU_SOFTRST_CON02(Offset:0xA08) 388 #define SRST_HRESETN_SDMMC0 0x000c0020 389 #define SRST_PRESETN_CSIPHY 0x000c0022 390 #define SRST_PRESETN_GPIO1 0x000c0023 391 #define SRST_DBRESETN_GPIO1 0x000c0024 392 #define SRST_PRESETN_IOC_VCCIO47 0x000c0025 393 #define SRST_PRESETN_VI_GRF 0x000c0026 394 #define SRST_PRESETN_CRU_VI 0x000c0028 395 #define SRST_PRESETN_VI_PVTPLL 0x000c0029 396 397 // ======================= CORECRU module definition bank=4 ======================= 398 // CORECRU_SOFTRST_CON00(Offset:0xA00) 399 #define SRST_RESETN_REF_PVTPLL_CORE 0x00100000 400 #define SRST_NCOREPORESET 0x00100001 401 #define SRST_NCORESET 0x00100002 402 #define SRST_NDBGRESET 0x00100003 403 #define SRST_NL2RESET 0x00100004 404 #define SRST_ARESETN_CORE_BIU 0x00100005 405 #define SRST_PRESETN_CORE_BIU 0x00100006 406 #define SRST_HRESETN_CORE_BIU 0x00100007 407 #define SRST_PRESETN_DBG 0x00100008 408 #define SRST_POTRESETN_DBG 0x00100009 409 #define SRST_NTRESETN_DBG 0x0010000A 410 411 // ======================= DDRCRU module definition bank=5 ======================== 412 // DDRCRU_SOFTRST_CON00(Offset:0xA00) 413 #define SRST_LSRESETN_DDR_BIU 0x00140001 414 #define SRST_PRESETN_DDRC 0x00140002 415 #define SRST_PRESETN_DDRMON 0x00140003 416 #define SRST_RESETN_TIMER_DDRMON 0x00140004 417 #define SRST_PRESETN_DFICTRL 0x00140005 418 #define SRST_PRESETN_DDR_GRF 0x00140006 419 #define SRST_PRESETN_CRU_DDR 0x00140007 420 #define SRST_HRESETN_DDRPHY 0x00140008 421 422 // ====================== SUBDDRCRU module definition bank=6 ====================== 423 // SUBDDRCRU_SOFTRST_CON00(Offset:0xA00) 424 #define SRST_RESETN_DDR_BIU 0x00160001 425 #define SRST_ARESETN_DDRSCH_CPU 0x00160002 426 #define SRST_ARESETN_DDRSCH_VI 0x00160004 427 #define SRST_ARESETN_DDRSCH_NPVD 0x00160005 428 #define SRST_RESETN_CORE_DDRC 0x00160006 429 #define SRST_RESETN_DDRMON 0x00160007 430 #define SRST_RESETN_DFICTRL 0x00160008 431 #define SRST_RESETN_DFI_SCRAMBLE 0x00160009 432 433 // ======================= TOPCRU module definition bank=7 ======================== 434 // TOPCRU_SOFTRST_CON00(Offset:0xA00) 435 #define SRST_PRESETN_CRU 0x00180000 436 #define SRST_PRESETN_CRU_BIU 0x00180001 437 #define SRST_RESETN_DDRPHY 0x0018000C 438 439 //======================= PMUCRU module definition bank=8 ======================== 440 // PMUCRU_SOFTRST_CON00(Offset:0xA00) 441 #define SRST_PRESETN_PMU_GPIO0 0x001c0004 442 #define SRST_DBRESETN_PMU_GPIO0 0x001c0005 443 #define SRST_RESETN_DDR_FAIL_SAFE 0x001c0008 444 #define SRST_PRESETN_PMU_HP_TIMER 0x001c0009 445 #define SRST_RESETN_PMU_HP_TIMER 0x001c000A 446 #define SRST_RESETN_PMU_32K_HP_TIMER 0x001c000B 447 #define SRST_PRESETN_I2C0 0x001c000C 448 #define SRST_RESETN_I2C0 0x001c000D 449 #define SRST_PRESETN_UART0 0x001c000E 450 #define SRST_SRESETN_UART0 0x001c000F 451 452 // PMUCRU_SOFTRST_CON01(Offset:0xA04) 453 #define SRST_PRESETN_IOC_PMUIO0 0x001c0010 454 #define SRST_PRESETN_CRU_PMU 0x001c0011 455 #define SRST_PRESETN_PMU_GRF 0x001c0012 456 #define SRST_PRESETN_PMU_SGRF 0x001c0013 457 #define SRST_PRESETN_PMU_SGRF_REMAP 0x001c0014 458 #define SRST_RESETN_PREROLL 0x001c0016 459 #define SRST_RESETN_PREROLL_32K 0x001c0017 460 #define SRST_HRESETN_PMU_SRAM 0x001c0018 461 #define SRST_PRESETN_PWM0 0x001c0019 462 #define SRST_RESETN_PWM0 0x001c001A 463 464 // PMUCRU_SOFTRST_CON02(Offset:0xA08) 465 #define SRST_RESETN_LPMCU 0x001c0020 466 #define SRST_RESETN_LPMCU_PWRUP 0x001c0021 467 #define SRST_RESETN_LPMCU_CPU 0x001c0022 468 #define SRST_TRESETN_LPMCU_CPU 0x001c0023 469 470 // ======================= PMU1CRU module definition bank=9 ======================= 471 // PMU1CRU_SOFTRST_CON00(Offset:0xA00) 472 #define SRST_PRESETN_SPI2AHB 0x00200000 473 #define SRST_HRESETN_SPI2AHB 0x00200001 474 #define SRST_SRESETN_SPI2AHB 0x00200002 475 #define SRST_LSRESETN_PMU_BIU 0x00200003 476 #define SRST_PRESETN_WDT_LPMCU 0x00200009 477 #define SRST_TRESETN_WDT_LPMCU 0x0020000A 478 #define SRST_HRESETN_SFC_PMU1 0x0020000C 479 #define SRST_HRESETN_SFC_XIP_PMU1 0x0020000D 480 #define SRST_SRESETN_SFC_2X_PMU1 0x0020000E 481 482 // PMU1CRU_SOFTRST_CON01(Offset:0xA04) 483 #define SRST_PRESETN_LPMCU_MAILBOX 0x00200018 484 #define SRST_PRESETN_IOC_PMUIO1 0x00200019 485 #define SRST_PRESETN_CRU_PMU1 0x0020001A 486 487 #define CLK_NR_SRST (SRST_PRESETN_CRU_PMU1 + 1) 488 489 #endif 490