1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 9 10 /* pmucru-clocks indices */ 11 12 /* pmucru plls */ 13 #define PLL_PPLL 1 14 #define PLL_HPLL 2 15 16 /* pmucru clocks */ 17 #define XIN_OSC0_DIV 4 18 #define CLK_RTC_32K 5 19 #define CLK_PMU 6 20 #define CLK_I2C0 7 21 #define CLK_RTC32K_FRAC 8 22 #define CLK_UART0_DIV 9 23 #define CLK_UART0_FRAC 10 24 #define SCLK_UART0 11 25 #define DBCLK_GPIO0 12 26 #define CLK_PWM0 13 27 #define CLK_CAPTURE_PWM0_NDFT 14 28 #define CLK_PMUPVTM 15 29 #define CLK_CORE_PMUPVTM 16 30 #define CLK_REF24M 17 31 #define XIN_OSC0_USBPHY0_G 18 32 #define CLK_USBPHY0_REF 19 33 #define XIN_OSC0_USBPHY1_G 20 34 #define CLK_USBPHY1_REF 21 35 #define XIN_OSC0_MIPIDSIPHY0_G 22 36 #define CLK_MIPIDSIPHY0_REF 23 37 #define XIN_OSC0_MIPIDSIPHY1_G 24 38 #define CLK_MIPIDSIPHY1_REF 25 39 #define CLK_WIFI_DIV 26 40 #define CLK_WIFI_OSC0 27 41 #define CLK_WIFI 28 42 #define CLK_PCIEPHY0_DIV 29 43 #define CLK_PCIEPHY0_OSC0 30 44 #define CLK_PCIEPHY0_REF 31 45 #define CLK_PCIEPHY1_DIV 32 46 #define CLK_PCIEPHY1_OSC0 33 47 #define CLK_PCIEPHY1_REF 34 48 #define CLK_PCIEPHY2_DIV 35 49 #define CLK_PCIEPHY2_OSC0 36 50 #define CLK_PCIEPHY2_REF 37 51 #define CLK_PCIE30PHY_REF_M 38 52 #define CLK_PCIE30PHY_REF_N 39 53 #define CLK_HDMI_REF 40 54 #define XIN_OSC0_EDPPHY_G 41 55 #define PCLK_PDPMU 42 56 #define PCLK_PMU 43 57 #define PCLK_UART0 44 58 #define PCLK_I2C0 45 59 #define PCLK_GPIO0 46 60 #define PCLK_PMUPVTM 47 61 #define PCLK_PWM0 48 62 63 #define CLKPMU_NR_CLKS (PCLK_PWM0 + 1) 64 65 /* cru-clocks indices */ 66 67 /* cru plls */ 68 #define PLL_APLL 1 69 #define PLL_DPLL 2 70 #define PLL_CPLL 3 71 #define PLL_GPLL 4 72 #define PLL_VPLL 5 73 #define PLL_NPLL 6 74 75 /* cru clocks */ 76 #define CPLL_333M 9 77 #define ARMCLK 10 78 #define USB480M 11 79 #define ACLK_CORE_NIU2BUS 18 80 #define CLK_CORE_PVTM 19 81 #define CLK_CORE_PVTM_CORE 20 82 #define CLK_CORE_PVTPLL 21 83 #define CLK_GPU_SRC 22 84 #define CLK_GPU_PRE_NDFT 23 85 #define CLK_GPU_PRE_MUX 24 86 #define ACLK_GPU_PRE 25 87 #define PCLK_GPU_PRE 26 88 #define CLK_GPU 27 89 #define CLK_GPU_NP5 28 90 #define PCLK_GPU_PVTM 29 91 #define CLK_GPU_PVTM 30 92 #define CLK_GPU_PVTM_CORE 31 93 #define CLK_GPU_PVTPLL 32 94 #define CLK_NPU_SRC 33 95 #define CLK_NPU_PRE_NDFT 34 96 #define CLK_NPU 35 97 #define CLK_NPU_NP5 36 98 #define HCLK_NPU_PRE 37 99 #define PCLK_NPU_PRE 38 100 #define ACLK_NPU_PRE 39 101 #define ACLK_NPU 40 102 #define HCLK_NPU 41 103 #define PCLK_NPU_PVTM 42 104 #define CLK_NPU_PVTM 43 105 #define CLK_NPU_PVTM_CORE 44 106 #define CLK_NPU_PVTPLL 45 107 #define CLK_DDRPHY1X_SRC 46 108 #define CLK_DDRPHY1X_HWFFC_SRC 47 109 #define CLK_DDR1X 48 110 #define CLK_MSCH 49 111 #define CLK24_DDRMON 50 112 #define ACLK_GIC_AUDIO 51 113 #define HCLK_GIC_AUDIO 52 114 #define HCLK_SDMMC_BUFFER 53 115 #define DCLK_SDMMC_BUFFER 54 116 #define ACLK_GIC600 55 117 #define ACLK_SPINLOCK 56 118 #define HCLK_I2S0_8CH 57 119 #define HCLK_I2S1_8CH 58 120 #define HCLK_I2S2_2CH 59 121 #define HCLK_I2S3_2CH 60 122 #define CLK_I2S0_8CH_TX_SRC 61 123 #define CLK_I2S0_8CH_TX_FRAC 62 124 #define MCLK_I2S0_8CH_TX 63 125 #define I2S0_MCLKOUT_TX 64 126 #define CLK_I2S0_8CH_RX_SRC 65 127 #define CLK_I2S0_8CH_RX_FRAC 66 128 #define MCLK_I2S0_8CH_RX 67 129 #define I2S0_MCLKOUT_RX 68 130 #define CLK_I2S1_8CH_TX_SRC 69 131 #define CLK_I2S1_8CH_TX_FRAC 70 132 #define MCLK_I2S1_8CH_TX 71 133 #define I2S1_MCLKOUT_TX 72 134 #define CLK_I2S1_8CH_RX_SRC 73 135 #define CLK_I2S1_8CH_RX_FRAC 74 136 #define MCLK_I2S1_8CH_RX 75 137 #define I2S1_MCLKOUT_RX 76 138 #define CLK_I2S2_2CH_SRC 77 139 #define CLK_I2S2_2CH_FRAC 78 140 #define MCLK_I2S2_2CH 79 141 #define I2S2_MCLKOUT 80 142 #define CLK_I2S3_2CH_TX_SRC 81 143 #define CLK_I2S3_2CH_TX_FRAC 82 144 #define MCLK_I2S3_2CH_TX 83 145 #define I2S3_MCLKOUT_TX 84 146 #define CLK_I2S3_2CH_RX_SRC 85 147 #define CLK_I2S3_2CH_RX_FRAC 86 148 #define MCLK_I2S3_2CH_RX 87 149 #define I2S3_MCLKOUT_RX 88 150 #define HCLK_PDM 89 151 #define MCLK_PDM 90 152 #define HCLK_VAD 91 153 #define HCLK_SPDIF_8CH 92 154 #define MCLK_SPDIF_8CH_SRC 93 155 #define MCLK_SPDIF_8CH_FRAC 94 156 #define MCLK_SPDIF_8CH 95 157 #define HCLK_AUDPWM 96 158 #define SCLK_AUDPWM_SRC 97 159 #define SCLK_AUDPWM_FRAC 98 160 #define SCLK_AUDPWM 99 161 #define HCLK_ACDCDIG 100 162 #define CLK_ACDCDIG_I2C 101 163 #define CLK_ACDCDIG_DAC 102 164 #define CLK_ACDCDIG_ADC 103 165 #define ACLK_SECURE_FLASH 104 166 #define HCLK_SECURE_FLASH 105 167 #define ACLK_CRYPTO_NS 106 168 #define HCLK_CRYPTO_NS 107 169 #define CLK_CRYPTO_NS_CORE 108 170 #define CLK_CRYPTO_NS_PKA 109 171 #define CLK_CRYPTO_NS_RNG 110 172 #define HCLK_TRNG_NS 111 173 #define CLK_TRNG_NS 112 174 #define PCLK_OTPC_NS 113 175 #define CLK_OTPC_NS_SBPI 114 176 #define CLK_OTPC_NS_USR 115 177 #define HCLK_NANDC 116 178 #define NCLK_NANDC 117 179 #define HCLK_SFC 118 180 #define HCLK_SFC_XIP 119 181 #define SCLK_SFC 120 182 #define ACLK_EMMC 121 183 #define HCLK_EMMC 122 184 #define BCLK_EMMC 123 185 #define CCLK_EMMC 124 186 #define TCLK_EMMC 125 187 #define ACLK_PIPE 126 188 #define PCLK_PIPE 127 189 #define PCLK_PIPE_GRF 128 190 #define ACLK_PCIE20_MST 129 191 #define ACLK_PCIE20_SLV 130 192 #define ACLK_PCIE20_DBI 131 193 #define PCLK_PCIE20 132 194 #define CLK_PCIE20_AUX_NDFT 133 195 #define CLK_PCIE20_AUX_DFT 134 196 #define CLK_PCIE20_PIPE_DFT 135 197 #define ACLK_PCIE30X1_MST 136 198 #define ACLK_PCIE30X1_SLV 137 199 #define ACLK_PCIE30X1_DBI 138 200 #define PCLK_PCIE30X1 139 201 #define CLK_PCIE30X1_AUX_NDFT 140 202 #define CLK_PCIE30X1_AUX_DFT 141 203 #define CLK_PCIE30X1_PIPE_DFT 142 204 #define ACLK_PCIE30X2_MST 143 205 #define ACLK_PCIE30X2_SLV 144 206 #define ACLK_PCIE30X2_DBI 145 207 #define PCLK_PCIE30X2 146 208 #define CLK_PCIE30X2_AUX_NDFT 147 209 #define CLK_PCIE30X2_AUX_DFT 148 210 #define CLK_PCIE30X2_PIPE_DFT 149 211 #define ACLK_SATA0 150 212 #define CLK_SATA0_PMALIVE 151 213 #define CLK_SATA0_RXOOB 152 214 #define CLK_SATA0_PIPE_NDFT 153 215 #define CLK_SATA0_PIPE_DFT 154 216 #define ACLK_SATA1 155 217 #define CLK_SATA1_PMALIVE 156 218 #define CLK_SATA1_RXOOB 157 219 #define CLK_SATA1_PIPE_NDFT 158 220 #define CLK_SATA1_PIPE_DFT 159 221 #define ACLK_SATA2 160 222 #define CLK_SATA2_PMALIVE 161 223 #define CLK_SATA2_RXOOB 162 224 #define CLK_SATA2_PIPE_NDFT 163 225 #define CLK_SATA2_PIPE_DFT 164 226 #define ACLK_USB3OTG0 165 227 #define CLK_USB3OTG0_REF 166 228 #define CLK_USB3OTG0_SUSPEND 167 229 #define ACLK_USB3OTG1 168 230 #define CLK_USB3OTG1_REF 169 231 #define CLK_USB3OTG1_SUSPEND 170 232 #define CLK_XPCS_EEE 171 233 #define PCLK_XPCS 172 234 #define ACLK_PHP 173 235 #define HCLK_PHP 174 236 #define PCLK_PHP 175 237 #define HCLK_SDMMC0 176 238 #define CLK_SDMMC0 177 239 #define HCLK_SDMMC1 178 240 #define CLK_SDMMC1 179 241 #define ACLK_GMAC0 180 242 #define PCLK_GMAC0 181 243 #define CLK_MAC0_2TOP 182 244 #define CLK_MAC0_OUT 183 245 #define CLK_MAC0_REFOUT 184 246 #define CLK_GMAC0_PTP_REF 185 247 #define ACLK_USB 186 248 #define HCLK_USB 187 249 #define PCLK_USB 188 250 #define HCLK_USB2HOST0 189 251 #define HCLK_USB2HOST0_ARB 190 252 #define HCLK_USB2HOST1 191 253 #define HCLK_USB2HOST1_ARB 192 254 #define HCLK_SDMMC2 193 255 #define CLK_SDMMC2 194 256 #define ACLK_GMAC1 195 257 #define PCLK_GMAC1 196 258 #define CLK_MAC1_2TOP 197 259 #define CLK_MAC1_OUT 198 260 #define CLK_MAC1_REFOUT 199 261 #define CLK_GMAC1_PTP_REF 200 262 #define ACLK_PERIMID 201 263 #define HCLK_PERIMID 202 264 #define ACLK_VI 203 265 #define HCLK_VI 204 266 #define PCLK_VI 205 267 #define ACLK_VICAP 206 268 #define HCLK_VICAP 207 269 #define DCLK_VICAP 208 270 #define ICLK_VICAP_G 209 271 #define ACLK_ISP 210 272 #define HCLK_ISP 211 273 #define CLK_ISP 212 274 #define PCLK_CSI2HOST1 213 275 #define CLK_CIF_OUT 214 276 #define CLK_CAM0_OUT 215 277 #define CLK_CAM1_OUT 216 278 #define ACLK_VO 217 279 #define HCLK_VO 218 280 #define PCLK_VO 219 281 #define ACLK_VOP_PRE 220 282 #define ACLK_VOP 221 283 #define HCLK_VOP 222 284 #define DCLK_VOP0 223 285 #define DCLK_VOP1 224 286 #define DCLK_VOP2 225 287 #define CLK_VOP_PWM 226 288 #define ACLK_HDCP 227 289 #define HCLK_HDCP 228 290 #define PCLK_HDCP 229 291 #define PCLK_HDMI_HOST 230 292 #define CLK_HDMI_SFR 231 293 #define CLK_HDMI_CEC 231 294 #define PCLK_DSITX_0 232 295 #define PCLK_DSITX_1 233 296 #define PCLK_EDP_CTRL 234 297 #define CLK_EDP_200M 235 298 #define ACLK_VPU_PRE 236 299 #define HCLK_VPU_PRE 237 300 #define ACLK_VPU 238 301 #define HCLK_VPU 239 302 #define ACLK_RGA_PRE 240 303 #define HCLK_RGA_PRE 241 304 #define PCLK_RGA_PRE 242 305 #define ACLK_RGA 243 306 #define HCLK_RGA 244 307 #define CLK_RGA_CORE 245 308 #define ACLK_IEP 246 309 #define HCLK_IEP 247 310 #define CLK_IEP_CORE 248 311 #define HCLK_EBC 249 312 #define DCLK_EBC 250 313 #define ACLK_JDEC 251 314 #define HCLK_JDEC 252 315 #define ACLK_JENC 253 316 #define HCLK_JENC 254 317 #define PCLK_EINK 255 318 #define HCLK_EINK 256 319 #define ACLK_RKVENC_PRE 257 320 #define HCLK_RKVENC_PRE 258 321 #define ACLK_RKVENC 259 322 #define HCLK_RKVENC 260 323 #define CLK_RKVENC_CORE 261 324 #define ACLK_RKVDEC_PRE 262 325 #define HCLK_RKVDEC_PRE 263 326 #define ACLK_RKVDEC 264 327 #define HCLK_RKVDEC 265 328 #define CLK_RKVDEC_CA 266 329 #define CLK_RKVDEC_CORE 267 330 #define CLK_RKVDEC_HEVC_CA 268 331 #define ACLK_BUS 269 332 #define PCLK_BUS 270 333 #define PCLK_TSADC 271 334 #define CLK_TSADC_TSEN 272 335 #define CLK_TSADC 273 336 #define PCLK_SARADC 274 337 #define CLK_SARADC 275 338 #define PCLK_SCR 276 339 #define PCLK_WDT_NS 277 340 #define TCLK_WDT_NS 278 341 #define ACLK_DMAC0 279 342 #define ACLK_DMAC1 280 343 #define ACLK_MCU 281 344 #define PCLK_INTMUX 282 345 #define PCLK_MAILBOX 283 346 #define PCLK_UART1 284 347 #define CLK_UART1_SRC 285 348 #define CLK_UART1_FRAC 286 349 #define SCLK_UART1 287 350 #define PCLK_UART2 288 351 #define CLK_UART2_SRC 289 352 #define CLK_UART2_FRAC 290 353 #define SCLK_UART2 291 354 #define PCLK_UART3 292 355 #define CLK_UART3_SRC 293 356 #define CLK_UART3_FRAC 294 357 #define SCLK_UART3 295 358 #define PCLK_UART4 296 359 #define CLK_UART4_SRC 297 360 #define CLK_UART4_FRAC 298 361 #define SCLK_UART4 299 362 #define PCLK_UART5 300 363 #define CLK_UART5_SRC 301 364 #define CLK_UART5_FRAC 302 365 #define SCLK_UART5 303 366 #define PCLK_UART6 304 367 #define CLK_UART6_SRC 305 368 #define CLK_UART6_FRAC 306 369 #define SCLK_UART6 307 370 #define PCLK_UART7 308 371 #define CLK_UART7_SRC 309 372 #define CLK_UART7_FRAC 310 373 #define SCLK_UART7 311 374 #define PCLK_UART8 312 375 #define CLK_UART8_SRC 313 376 #define CLK_UART8_FRAC 314 377 #define SCLK_UART8 315 378 #define PCLK_UART9 316 379 #define CLK_UART9_SRC 317 380 #define CLK_UART9_FRAC 318 381 #define SCLK_UART9 319 382 #define PCLK_CAN0 320 383 #define CLK_CAN0 321 384 #define PCLK_CAN1 322 385 #define CLK_CAN1 323 386 #define PCLK_CAN2 324 387 #define CLK_CAN2 325 388 #define CLK_I2C 326 389 #define PCLK_I2C1 327 390 #define CLK_I2C1 328 391 #define PCLK_I2C2 329 392 #define CLK_I2C2 330 393 #define PCLK_I2C3 331 394 #define CLK_I2C3 332 395 #define PCLK_I2C4 333 396 #define CLK_I2C4 334 397 #define PCLK_I2C5 335 398 #define CLK_I2C5 336 399 #define PCLK_SPI0 337 400 #define CLK_SPI0 338 401 #define PCLK_SPI1 339 402 #define CLK_SPI1 340 403 #define PCLK_SPI2 341 404 #define CLK_SPI2 342 405 #define PCLK_SPI3 343 406 #define CLK_SPI3 344 407 #define PCLK_PWM1 345 408 #define CLK_PWM1 346 409 #define CLK_PWM1_CAPTURE 347 410 #define PCLK_PWM2 348 411 #define CLK_PWM2 349 412 #define CLK_PWM2_CAPTURE 350 413 #define PCLK_PWM3 351 414 #define CLK_PWM3 352 415 #define CLK_PWM3_CAPTURE 353 416 #define DBCLK_GPIO 354 417 #define PCLK_GPIO1 355 418 #define DBCLK_GPIO1 356 419 #define PCLK_GPIO2 357 420 #define DBCLK_GPIO2 358 421 #define PCLK_GPIO3 359 422 #define DBCLK_GPIO3 360 423 #define PCLK_GPIO4 361 424 #define DBCLK_GPIO4 362 425 #define OCC_SCAN_CLK_GPIO 363 426 #define PCLK_TIMER 364 427 #define CLK_TIMER0 365 428 #define CLK_TIMER1 366 429 #define CLK_TIMER2 367 430 #define CLK_TIMER3 368 431 #define CLK_TIMER4 369 432 #define CLK_TIMER5 370 433 #define ACLK_TOP_HIGH 371 434 #define ACLK_TOP_LOW 372 435 #define HCLK_TOP 373 436 #define PCLK_TOP 374 437 #define PCLK_PCIE30PHY 375 438 #define CLK_OPTC_ARB 376 439 #define PCLK_MIPICSIPHY 377 440 #define PCLK_MIPIDSIPHY0 378 441 #define PCLK_MIPIDSIPHY1 379 442 #define PCLK_PIPEPHY0 380 443 #define PCLK_PIPEPHY1 381 444 #define PCLK_PIPEPHY2 382 445 #define PCLK_CPU_BOOST 383 446 #define CLK_CPU_BOOST 384 447 #define PCLK_OTPPHY 385 448 #define SCLK_GMAC0 386 449 #define SCLK_GMAC0_RGMII_SPEED 387 450 #define SCLK_GMAC0_RMII_SPEED 388 451 #define SCLK_GMAC0_RX_TX 389 452 #define SCLK_GMAC1 390 453 #define SCLK_GMAC1_RGMII_SPEED 391 454 #define SCLK_GMAC1_RMII_SPEED 392 455 #define SCLK_GMAC1_RX_TX 393 456 #define SCLK_SDMMC0_DRV 394 457 #define SCLK_SDMMC0_SAMPLE 395 458 #define SCLK_SDMMC1_DRV 396 459 #define SCLK_SDMMC1_SAMPLE 397 460 #define SCLK_SDMMC2_DRV 398 461 #define SCLK_SDMMC2_SAMPLE 399 462 #define SCLK_EMMC_DRV 400 463 #define SCLK_EMMC_SAMPLE 401 464 #define PCLK_EDPPHY_GRF 402 465 #define PCLK_CORE_PVTM 403 466 467 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) 468 469 /* pmu soft-reset indices */ 470 /* pmucru_softrst_con0 */ 471 #define SRST_P_PDPMU_NIU 0 472 #define SRST_P_PMUCRU 1 473 #define SRST_P_PMUGRF 2 474 #define SRST_P_I2C0 3 475 #define SRST_I2C0 4 476 #define SRST_P_UART0 5 477 #define SRST_S_UART0 6 478 #define SRST_P_PWM0 7 479 #define SRST_PWM0 8 480 #define SRST_P_GPIO0 9 481 #define SRST_GPIO0 10 482 #define SRST_P_PMUPVTM 11 483 #define SRST_PMUPVTM 12 484 485 /* soft-reset indices */ 486 487 /* cru_softrst_con0 */ 488 #define SRST_NCORERESET0 0 489 #define SRST_NCORERESET1 1 490 #define SRST_NCORERESET2 2 491 #define SRST_NCORERESET3 3 492 #define SRST_NCPUPORESET0 4 493 #define SRST_NCPUPORESET1 5 494 #define SRST_NCPUPORESET2 6 495 #define SRST_NCPUPORESET3 7 496 #define SRST_NSRESET 8 497 #define SRST_NSPORESET 9 498 #define SRST_NATRESET 10 499 #define SRST_NGICRESET 11 500 #define SRST_NPRESET 12 501 #define SRST_NPERIPHRESET 13 502 503 /* cru_softrst_con1 */ 504 #define SRST_A_CORE_NIU2DDR 16 505 #define SRST_A_CORE_NIU2BUS 17 506 #define SRST_P_DBG_NIU 18 507 #define SRST_P_DBG 19 508 #define SRST_P_DBG_DAPLITE 20 509 #define SRST_DAP 21 510 #define SRST_A_ADB400_CORE2GIC 22 511 #define SRST_A_ADB400_GIC2CORE 23 512 #define SRST_P_CORE_GRF 24 513 #define SRST_P_CORE_PVTM 25 514 #define SRST_CORE_PVTM 26 515 #define SRST_CORE_PVTPLL 27 516 517 /* cru_softrst_con2 */ 518 #define SRST_GPU 32 519 #define SRST_A_GPU_NIU 33 520 #define SRST_P_GPU_NIU 34 521 #define SRST_P_GPU_PVTM 35 522 #define SRST_GPU_PVTM 36 523 #define SRST_GPU_PVTPLL 37 524 #define SRST_A_NPU_NIU 40 525 #define SRST_H_NPU_NIU 41 526 #define SRST_P_NPU_NIU 42 527 #define SRST_A_NPU 43 528 #define SRST_H_NPU 44 529 #define SRST_P_NPU_PVTM 45 530 #define SRST_NPU_PVTM 46 531 #define SRST_NPU_PVTPLL 47 532 533 /* cru_softrst_con3 */ 534 #define SRST_A_MSCH 51 535 #define SRST_HWFFC_CTRL 52 536 #define SRST_DDR_ALWAYSON 53 537 #define SRST_A_DDRSPLIT 54 538 #define SRST_DDRDFI_CTL 55 539 #define SRST_A_DMA2DDR 57 540 541 /* cru_softrst_con4 */ 542 #define SRST_A_PERIMID_NIU 64 543 #define SRST_H_PERIMID_NIU 65 544 #define SRST_A_GIC_AUDIO_NIU 66 545 #define SRST_H_GIC_AUDIO_NIU 67 546 #define SRST_A_GIC600 68 547 #define SRST_A_GIC600_DEBUG 69 548 #define SRST_A_GICADB_CORE2GIC 70 549 #define SRST_A_GICADB_GIC2CORE 71 550 #define SRST_A_SPINLOCK 72 551 #define SRST_H_SDMMC_BUFFER 73 552 #define SRST_D_SDMMC_BUFFER 74 553 #define SRST_H_I2S0_8CH 75 554 #define SRST_H_I2S1_8CH 76 555 #define SRST_H_I2S2_2CH 77 556 #define SRST_H_I2S3_2CH 78 557 558 /* cru_softrst_con5 */ 559 #define SRST_M_I2S0_8CH_TX 80 560 #define SRST_M_I2S0_8CH_RX 81 561 #define SRST_M_I2S1_8CH_TX 82 562 #define SRST_M_I2S1_8CH_RX 83 563 #define SRST_M_I2S2_2CH 84 564 #define SRST_M_I2S3_2CH_TX 85 565 #define SRST_M_I2S3_2CH_RX 86 566 #define SRST_H_PDM 87 567 #define SRST_M_PDM 88 568 #define SRST_H_VAD 89 569 #define SRST_H_SPDIF_8CH 90 570 #define SRST_M_SPDIF_8CH 91 571 #define SRST_H_AUDPWM 92 572 #define SRST_S_AUDPWM 93 573 #define SRST_H_ACDCDIG 94 574 #define SRST_ACDCDIG 95 575 576 /* cru_softrst_con6 */ 577 #define SRST_A_SECURE_FLASH_NIU 96 578 #define SRST_H_SECURE_FLASH_NIU 97 579 #define SRST_A_CRYPTO_NS 103 580 #define SRST_H_CRYPTO_NS 104 581 #define SRST_CRYPTO_NS_CORE 105 582 #define SRST_CRYPTO_NS_PKA 106 583 #define SRST_CRYPTO_NS_RNG 107 584 #define SRST_H_TRNG_NS 108 585 #define SRST_TRNG_NS 109 586 587 /* cru_softrst_con7 */ 588 #define SRST_H_NANDC 112 589 #define SRST_N_NANDC 113 590 #define SRST_H_SFC 114 591 #define SRST_H_SFC_XIP 115 592 #define SRST_S_SFC 116 593 #define SRST_A_EMMC 117 594 #define SRST_H_EMMC 118 595 #define SRST_B_EMMC 119 596 #define SRST_C_EMMC 120 597 #define SRST_T_EMMC 121 598 599 /* cru_softrst_con8 */ 600 #define SRST_A_PIPE_NIU 128 601 #define SRST_P_PIPE_NIU 130 602 #define SRST_P_PIPE_GRF 133 603 #define SRST_A_SATA0 134 604 #define SRST_SATA0_PIPE 135 605 #define SRST_SATA0_PMALIVE 136 606 #define SRST_SATA0_RXOOB 137 607 #define SRST_A_SATA1 138 608 #define SRST_SATA1_PIPE 139 609 #define SRST_SATA1_PMALIVE 140 610 #define SRST_SATA1_RXOOB 141 611 612 /* cru_softrst_con9 */ 613 #define SRST_A_SATA2 144 614 #define SRST_SATA2_PIPE 145 615 #define SRST_SATA2_PMALIVE 146 616 #define SRST_SATA2_RXOOB 147 617 #define SRST_USB3OTG0 148 618 #define SRST_USB3OTG1 149 619 #define SRST_XPCS 150 620 #define SRST_XPCS_TX_DIV10 151 621 #define SRST_XPCS_RX_DIV10 152 622 #define SRST_XPCS_XGXS_RX 153 623 624 /* cru_softrst_con10 */ 625 #define SRST_P_PCIE20 160 626 627 /* cru_softrst_con11 */ 628 #define SRST_P_PCIE30X1 176 629 630 /* cru_softrst_con12 */ 631 #define SRST_P_PCIE30X2 192 632 633 /* cru_softrst_con13 */ 634 #define SRST_A_PHP_NIU 208 635 #define SRST_H_PHP_NIU 209 636 #define SRST_P_PHP_NIU 210 637 #define SRST_H_SDMMC0 211 638 #define SRST_SDMMC0 212 639 #define SRST_H_SDMMC1 213 640 #define SRST_SDMMC1 214 641 #define SRST_A_GMAC0 215 642 #define SRST_GMAC0_TIMESTAMP 216 643 644 /* cru_softrst_con14 */ 645 #define SRST_A_USB_NIU 224 646 #define SRST_H_USB_NIU 225 647 #define SRST_P_USB_NIU 226 648 #define SRST_P_USB_GRF 227 649 #define SRST_H_USB2HOST0 228 650 #define SRST_H_USB2HOST0_ARB 229 651 #define SRST_USB2HOST0_UTMI 230 652 #define SRST_H_USB2HOST1 231 653 #define SRST_H_USB2HOST1_ARB 232 654 #define SRST_USB2HOST1_UTMI 233 655 #define SRST_H_SDMMC2 234 656 #define SRST_SDMMC2 235 657 #define SRST_A_GMAC1 236 658 #define SRST_GMAC1_TIMESTAMP 237 659 660 /* cru_softrst_con15 */ 661 #define SRST_A_VI_NIU 240 662 #define SRST_H_VI_NIU 241 663 #define SRST_P_VI_NIU 242 664 #define SRST_A_VICAP 247 665 #define SRST_H_VICAP 248 666 #define SRST_D_VICAP 249 667 #define SRST_I_VICAP 250 668 #define SRST_P_VICAP 251 669 #define SRST_H_ISP 252 670 #define SRST_ISP 253 671 #define SRST_P_CSI2HOST1 255 672 673 /* cru_softrst_con16 */ 674 #define SRST_A_VO_NIU 256 675 #define SRST_H_VO_NIU 257 676 #define SRST_P_VO_NIU 258 677 #define SRST_A_VOP_NIU 259 678 #define SRST_A_VOP 260 679 #define SRST_H_VOP 261 680 #define SRST_VOP0 262 681 #define SRST_VOP1 263 682 #define SRST_VOP2 264 683 #define SRST_VOP_PWM 265 684 #define SRST_A_HDCP 266 685 #define SRST_H_HDCP 267 686 #define SRST_P_HDCP 268 687 #define SRST_P_HDMI_HOST 270 688 #define SRST_HDMI_HOST 271 689 690 /* cru_softrst_con17 */ 691 #define SRST_P_DSITX_0 272 692 #define SRST_P_DSITX_1 273 693 #define SRST_P_EDP_CTRL 274 694 #define SRST_EDP_24M 275 695 #define SRST_A_VPU_NIU 280 696 #define SRST_H_VPU_NIU 281 697 #define SRST_A_VPU 282 698 #define SRST_H_VPU 283 699 #define SRST_H_EINK 286 700 #define SRST_P_EINK 287 701 702 /* cru_softrst_con18 */ 703 #define SRST_A_RGA_NIU 288 704 #define SRST_H_RGA_NIU 289 705 #define SRST_P_RGA_NIU 290 706 #define SRST_A_RGA 292 707 #define SRST_H_RGA 293 708 #define SRST_RGA_CORE 294 709 #define SRST_A_IEP 295 710 #define SRST_H_IEP 296 711 #define SRST_IEP_CORE 297 712 #define SRST_H_EBC 298 713 #define SRST_D_EBC 299 714 #define SRST_A_JDEC 300 715 #define SRST_H_JDEC 301 716 #define SRST_A_JENC 302 717 #define SRST_H_JENC 303 718 719 /* cru_softrst_con19 */ 720 #define SRST_A_VENC_NIU 304 721 #define SRST_H_VENC_NIU 305 722 #define SRST_A_RKVENC 307 723 #define SRST_H_RKVENC 308 724 #define SRST_RKVENC_CORE 309 725 726 /* cru_softrst_con20 */ 727 #define SRST_A_RKVDEC_NIU 320 728 #define SRST_H_RKVDEC_NIU 321 729 #define SRST_A_RKVDEC 322 730 #define SRST_H_RKVDEC 323 731 #define SRST_RKVDEC_CA 324 732 #define SRST_RKVDEC_CORE 325 733 #define SRST_RKVDEC_HEVC_CA 326 734 735 /* cru_softrst_con21 */ 736 #define SRST_A_BUS_NIU 336 737 #define SRST_P_BUS_NIU 338 738 #define SRST_P_CAN0 340 739 #define SRST_CAN0 341 740 #define SRST_P_CAN1 342 741 #define SRST_CAN1 343 742 #define SRST_P_CAN2 344 743 #define SRST_CAN2 345 744 #define SRST_P_GPIO1 346 745 #define SRST_GPIO1 347 746 #define SRST_P_GPIO2 348 747 #define SRST_GPIO2 349 748 #define SRST_P_GPIO3 350 749 #define SRST_GPIO3 351 750 751 /* cru_softrst_con22 */ 752 #define SRST_P_GPIO4 352 753 #define SRST_GPIO4 353 754 #define SRST_P_I2C1 354 755 #define SRST_I2C1 355 756 #define SRST_P_I2C2 356 757 #define SRST_I2C2 357 758 #define SRST_P_I2C3 358 759 #define SRST_I2C3 359 760 #define SRST_P_I2C4 360 761 #define SRST_I2C4 361 762 #define SRST_P_I2C5 362 763 #define SRST_I2C5 363 764 #define SRST_P_OTPC_NS 364 765 #define SRST_OTPC_NS_SBPI 365 766 #define SRST_OTPC_NS_USR 366 767 768 /* cru_softrst_con23 */ 769 #define SRST_P_PWM1 368 770 #define SRST_PWM1 369 771 #define SRST_P_PWM2 370 772 #define SRST_PWM2 371 773 #define SRST_P_PWM3 372 774 #define SRST_PWM3 373 775 #define SRST_P_SPI0 374 776 #define SRST_SPI0 375 777 #define SRST_P_SPI1 376 778 #define SRST_SPI1 377 779 #define SRST_P_SPI2 378 780 #define SRST_SPI2 379 781 #define SRST_P_SPI3 380 782 #define SRST_SPI3 381 783 784 /* cru_softrst_con24 */ 785 #define SRST_P_SARADC 384 786 #define SRST_P_TSADC 385 787 #define SRST_TSADC 386 788 #define SRST_P_TIMER 387 789 #define SRST_TIMER0 388 790 #define SRST_TIMER1 389 791 #define SRST_TIMER2 390 792 #define SRST_TIMER3 391 793 #define SRST_TIMER4 392 794 #define SRST_TIMER5 393 795 #define SRST_P_UART1 394 796 #define SRST_S_UART1 395 797 798 /* cru_softrst_con25 */ 799 #define SRST_P_UART2 400 800 #define SRST_S_UART2 401 801 #define SRST_P_UART3 402 802 #define SRST_S_UART3 403 803 #define SRST_P_UART4 404 804 #define SRST_S_UART4 405 805 #define SRST_P_UART5 406 806 #define SRST_S_UART5 407 807 #define SRST_P_UART6 408 808 #define SRST_S_UART6 409 809 #define SRST_P_UART7 410 810 #define SRST_S_UART7 411 811 #define SRST_P_UART8 412 812 #define SRST_S_UART8 413 813 #define SRST_P_UART9 414 814 #define SRST_S_UART9 415 815 816 /* cru_softrst_con26 */ 817 #define SRST_P_GRF 416 818 #define SRST_P_GRF_VCCIO12 417 819 #define SRST_P_GRF_VCCIO34 418 820 #define SRST_P_GRF_VCCIO567 419 821 #define SRST_P_SCR 420 822 #define SRST_P_WDT_NS 421 823 #define SRST_T_WDT_NS 422 824 #define SRST_P_DFT2APB 423 825 #define SRST_A_MCU 426 826 #define SRST_P_INTMUX 427 827 #define SRST_P_MAILBOX 428 828 829 /* cru_softrst_con27 */ 830 #define SRST_A_TOP_HIGH_NIU 432 831 #define SRST_A_TOP_LOW_NIU 433 832 #define SRST_H_TOP_NIU 434 833 #define SRST_P_TOP_NIU 435 834 #define SRST_P_TOP_CRU 438 835 #define SRST_P_DDRPHY 439 836 #define SRST_DDRPHY 440 837 #define SRST_P_MIPICSIPHY 442 838 #define SRST_P_MIPIDSIPHY0 443 839 #define SRST_P_MIPIDSIPHY1 444 840 #define SRST_P_PCIE30PHY 445 841 #define SRST_PCIE30PHY 446 842 #define SRST_P_PCIE30PHY_GRF 447 843 844 /* cru_softrst_con28 */ 845 #define SRST_P_APB2ASB_LEFT 448 846 #define SRST_P_APB2ASB_BOTTOM 449 847 #define SRST_P_ASB2APB_LEFT 450 848 #define SRST_P_ASB2APB_BOTTOM 451 849 #define SRST_P_PIPEPHY0 452 850 #define SRST_PIPEPHY0 453 851 #define SRST_P_PIPEPHY1 454 852 #define SRST_PIPEPHY1 455 853 #define SRST_P_PIPEPHY2 456 854 #define SRST_PIPEPHY2 457 855 #define SRST_P_USB2PHY0_GRF 458 856 #define SRST_P_USB2PHY1_GRF 459 857 #define SRST_P_CPU_BOOST 460 858 #define SRST_CPU_BOOST 461 859 #define SRST_P_OTPPHY 462 860 #define SRST_OTPPHY 463 861 862 /* cru_softrst_con29 */ 863 #define SRST_USB2PHY0_POR 464 864 #define SRST_USB2PHY0_USB3OTG0 465 865 #define SRST_USB2PHY0_USB3OTG1 466 866 #define SRST_USB2PHY1_POR 467 867 #define SRST_USB2PHY1_USB2HOST0 468 868 #define SRST_USB2PHY1_USB2HOST1 469 869 #define SRST_P_EDPPHY_GRF 470 870 #define SRST_TSADCPHY 471 871 #define SRST_GMAC0_DELAYLINE 472 872 #define SRST_GMAC1_DELAYLINE 473 873 #define SRST_OTPC_ARB 474 874 #define SRST_P_PIPEPHY0_GRF 475 875 #define SRST_P_PIPEPHY1_GRF 476 876 #define SRST_P_PIPEPHY2_GRF 477 877 878 #endif 879