1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 9 10 /* pmucru-clocks indices */ 11 12 /* pmucru plls */ 13 #define PLL_PPLL 1 14 #define PLL_HPLL 2 15 16 /* pmucru clocks */ 17 #define XIN_OSC0_DIV 4 18 #define CLK_RTC_32K 5 19 #define CLK_PMU 6 20 #define CLK_I2C0 7 21 #define CLK_RTC32K_FRAC 8 22 #define CLK_UART0_DIV 9 23 #define CLK_UART0_FRAC 10 24 #define SCLK_UART0 11 25 #define DBCLK_GPIO0 12 26 #define CLK_PWM0 13 27 #define CLK_CAPTURE_PWM0_NDFT 14 28 #define CLK_PMUPVTM 15 29 #define CLK_CORE_PMUPVTM 16 30 #define CLK_REF24M 17 31 #define XIN_OSC0_USBPHY0_G 18 32 #define CLK_USBPHY0_REF 19 33 #define XIN_OSC0_USBPHY1_G 20 34 #define CLK_USBPHY1_REF 21 35 #define XIN_OSC0_MIPIDSIPHY0_G 22 36 #define CLK_MIPIDSIPHY0_REF 23 37 #define XIN_OSC0_MIPIDSIPHY1_G 24 38 #define CLK_MIPIDSIPHY1_REF 25 39 #define CLK_WIFI_DIV 26 40 #define CLK_WIFI_OSC0 27 41 #define CLK_WIFI 28 42 #define CLK_PCIEPHY0_DIV 29 43 #define CLK_PCIEPHY0_OSC0 30 44 #define CLK_PCIEPHY0_REF 31 45 #define CLK_PCIEPHY1_DIV 32 46 #define CLK_PCIEPHY1_OSC0 33 47 #define CLK_PCIEPHY1_REF 34 48 #define CLK_PCIEPHY2_DIV 35 49 #define CLK_PCIEPHY2_OSC0 36 50 #define CLK_PCIEPHY2_REF 37 51 #define CLK_PCIE30PHY_REF_M 38 52 #define CLK_PCIE30PHY_REF_N 39 53 #define CLK_HDMI_REF 40 54 #define XIN_OSC0_EDPPHY_G 41 55 #define PCLK_PDPMU 42 56 #define PCLK_PMU 43 57 #define PCLK_UART0 44 58 #define PCLK_I2C0 45 59 #define PCLK_GPIO0 46 60 #define PCLK_PMUPVTM 47 61 #define PCLK_PWM0 48 62 63 #define CLKPMU_NR_CLKS (PCLK_PWM0 + 1) 64 65 /* cru-clocks indices */ 66 67 /* cru plls */ 68 #define PLL_APLL 1 69 #define PLL_DPLL 2 70 #define PLL_CPLL 3 71 #define PLL_GPLL 4 72 #define PLL_VPLL 5 73 #define PLL_NPLL 6 74 75 /* cru clocks */ 76 #define ARMCLK 10 77 #define USB480M 11 78 #define ACLK_CORE_NIU2BUS 18 79 #define CLK_CORE_PVTM 19 80 #define CLK_CORE_PVTM_CORE 20 81 #define CLK_CORE_PVTPLL 21 82 #define CLK_GPU_SRC 22 83 #define CLK_GPU_PRE_NDFT 23 84 #define CLK_GPU_PRE_MUX 24 85 #define ACLK_GPU_PRE 25 86 #define PCLK_GPU_PRE 26 87 #define CLK_GPU 27 88 #define CLK_GPU_NP5 28 89 #define PCLK_GPU_PVTM 29 90 #define CLK_GPU_PVTM 30 91 #define CLK_GPU_PVTM_CORE 31 92 #define CLK_GPU_PVTPLL 32 93 #define CLK_NPU_SRC 33 94 #define CLK_NPU_PRE_NDFT 34 95 #define CLK_NPU 35 96 #define CLK_NPU_NP5 36 97 #define HCLK_NPU_PRE 37 98 #define PCLK_NPU_PRE 38 99 #define ACLK_NPU_PRE 39 100 #define ACLK_NPU 40 101 #define HCLK_NPU 41 102 #define PCLK_NPU_PVTM 42 103 #define CLK_NPU_PVTM 43 104 #define CLK_NPU_PVTM_CORE 44 105 #define CLK_NPU_PVTPLL 45 106 #define CLK_DDRPHY1X_SRC 46 107 #define CLK_DDRPHY1X_HWFFC_SRC 47 108 #define CLK_DDR1X 48 109 #define CLK_MSCH 49 110 #define CLK24_DDRMON 50 111 #define ACLK_GIC_AUDIO 51 112 #define HCLK_GIC_AUDIO 52 113 #define HCLK_SDMMC_BUFFER 53 114 #define DCLK_SDMMC_BUFFER 54 115 #define ACLK_GIC600 55 116 #define ACLK_SPINLOCK 56 117 #define HCLK_I2S0_8CH 57 118 #define HCLK_I2S1_8CH 58 119 #define HCLK_I2S2_2CH 59 120 #define HCLK_I2S3_2CH 60 121 #define CLK_I2S0_8CH_TX_SRC 61 122 #define CLK_I2S0_8CH_TX_FRAC 62 123 #define MCLK_I2S0_8CH_TX 63 124 #define I2S0_MCLKOUT_TX 64 125 #define CLK_I2S0_8CH_RX_SRC 65 126 #define CLK_I2S0_8CH_RX_FRAC 66 127 #define MCLK_I2S0_8CH_RX 67 128 #define I2S0_MCLKOUT_RX 68 129 #define CLK_I2S1_8CH_TX_SRC 69 130 #define CLK_I2S1_8CH_TX_FRAC 70 131 #define MCLK_I2S1_8CH_TX 71 132 #define I2S1_MCLKOUT_TX 72 133 #define CLK_I2S1_8CH_RX_SRC 73 134 #define CLK_I2S1_8CH_RX_FRAC 74 135 #define MCLK_I2S1_8CH_RX 75 136 #define I2S1_MCLKOUT_RX 76 137 #define CLK_I2S2_2CH_SRC 77 138 #define CLK_I2S2_2CH_FRAC 78 139 #define MCLK_I2S2_2CH 79 140 #define I2S2_MCLKOUT 80 141 #define CLK_I2S3_2CH_TX_SRC 81 142 #define CLK_I2S3_2CH_TX_FRAC 82 143 #define MCLK_I2S3_2CH_TX 83 144 #define I2S3_MCLKOUT_TX 84 145 #define CLK_I2S3_2CH_RX_SRC 85 146 #define CLK_I2S3_2CH_RX_FRAC 86 147 #define MCLK_I2S3_2CH_RX 87 148 #define I2S3_MCLKOUT_RX 88 149 #define HCLK_PDM 89 150 #define MCLK_PDM 90 151 #define HCLK_VAD 91 152 #define HCLK_SPDIF_8CH 92 153 #define MCLK_SPDIF_8CH_SRC 93 154 #define MCLK_SPDIF_8CH_FRAC 94 155 #define MCLK_SPDIF_8CH 95 156 #define HCLK_AUDPWM 96 157 #define SCLK_AUDPWM_SRC 97 158 #define SCLK_AUDPWM_FRAC 98 159 #define SCLK_AUDPWM 99 160 #define HCLK_ACDCDIG 100 161 #define CLK_ACDCDIG_I2C 101 162 #define CLK_ACDCDIG_DAC 102 163 #define CLK_ACDCDIG_ADC 103 164 #define ACLK_SECURE_FLASH 104 165 #define HCLK_SECURE_FLASH 105 166 #define ACLK_CRYPTO_NS 106 167 #define HCLK_CRYPTO_NS 107 168 #define CLK_CRYPTO_NS_CORE 108 169 #define CLK_CRYPTO_NS_PKA 109 170 #define CLK_CRYPTO_NS_RNG 110 171 #define HCLK_TRNG_NS 111 172 #define CLK_TRNG_NS 112 173 #define PCLK_OTPC_NS 113 174 #define CLK_OTPC_NS_SBPI 114 175 #define CLK_OTPC_NS_USR 115 176 #define HCLK_NANDC 116 177 #define NCLK_NANDC 117 178 #define HCLK_SFC 118 179 #define HCLK_SFC_XIP 119 180 #define SCLK_SFC 120 181 #define ACLK_EMMC 121 182 #define HCLK_EMMC 122 183 #define BCLK_EMMC 123 184 #define CCLK_EMMC 124 185 #define TCLK_EMMC 125 186 #define ACLK_PIPE 126 187 #define PCLK_PIPE 127 188 #define PCLK_PIPE_GRF 128 189 #define ACLK_PCIE20_MST 129 190 #define ACLK_PCIE20_SLV 130 191 #define ACLK_PCIE20_DBI 131 192 #define PCLK_PCIE20 132 193 #define CLK_PCIE20_AUX_NDFT 133 194 #define CLK_PCIE20_AUX_DFT 134 195 #define CLK_PCIE20_PIPE_DFT 135 196 #define ACLK_PCIE30X1_MST 136 197 #define ACLK_PCIE30X1_SLV 137 198 #define ACLK_PCIE30X1_DBI 138 199 #define PCLK_PCIE30X1 139 200 #define CLK_PCIE30X1_AUX_NDFT 140 201 #define CLK_PCIE30X1_AUX_DFT 141 202 #define CLK_PCIE30X1_PIPE_DFT 142 203 #define ACLK_PCIE30X2_MST 143 204 #define ACLK_PCIE30X2_SLV 144 205 #define ACLK_PCIE30X2_DBI 145 206 #define PCLK_PCIE30X2 146 207 #define CLK_PCIE30X2_AUX_NDFT 147 208 #define CLK_PCIE30X2_AUX_DFT 148 209 #define CLK_PCIE30X2_PIPE_DFT 149 210 #define ACLK_SATA0 150 211 #define CLK_SATA0_PMALIVE 151 212 #define CLK_SATA0_RXOOB 152 213 #define CLK_SATA0_PIPE_NDFT 153 214 #define CLK_SATA0_PIPE_DFT 154 215 #define ACLK_SATA1 155 216 #define CLK_SATA1_PMALIVE 156 217 #define CLK_SATA1_RXOOB 157 218 #define CLK_SATA1_PIPE_NDFT 158 219 #define CLK_SATA1_PIPE_DFT 159 220 #define ACLK_SATA2 160 221 #define CLK_SATA2_PMALIVE 161 222 #define CLK_SATA2_RXOOB 162 223 #define CLK_SATA2_PIPE_NDFT 163 224 #define CLK_SATA2_PIPE_DFT 164 225 #define ACLK_USB3OTG0 165 226 #define CLK_USB3OTG0_REF 166 227 #define CLK_USB3OTG0_SUSPEND 167 228 #define ACLK_USB3OTG1 168 229 #define CLK_USB3OTG1_REF 169 230 #define CLK_USB3OTG1_SUSPEND 170 231 #define CLK_XPCS_EEE 171 232 #define PCLK_XPCS 172 233 #define ACLK_PHP 173 234 #define HCLK_PHP 174 235 #define PCLK_PHP 175 236 #define HCLK_SDMMC0 176 237 #define CLK_SDMMC0 177 238 #define HCLK_SDMMC1 178 239 #define CLK_SDMMC1 179 240 #define ACLK_GMAC0 180 241 #define PCLK_GMAC0 181 242 #define CLK_MAC0_2TOP 182 243 #define CLK_MAC0_OUT 183 244 #define CLK_MAC0_REFOUT 184 245 #define CLK_GMAC0_PTP_REF 185 246 #define ACLK_USB 186 247 #define HCLK_USB 187 248 #define PCLK_USB 188 249 #define HCLK_USB2HOST0 189 250 #define HCLK_USB2HOST0_ARB 190 251 #define HCLK_USB2HOST1 191 252 #define HCLK_USB2HOST1_ARB 192 253 #define HCLK_SDMMC2 193 254 #define CLK_SDMMC2 194 255 #define ACLK_GMAC1 195 256 #define PCLK_GMAC1 196 257 #define CLK_MAC1_2TOP 197 258 #define CLK_MAC1_OUT 198 259 #define CLK_MAC1_REFOUT 199 260 #define CLK_GMAC1_PTP_REF 200 261 #define ACLK_PERIMID 201 262 #define HCLK_PERIMID 202 263 #define ACLK_VI 203 264 #define HCLK_VI 204 265 #define PCLK_VI 205 266 #define ACLK_VICAP 206 267 #define HCLK_VICAP 207 268 #define DCLK_VICAP 208 269 #define ICLK_VICAP_G 209 270 #define ACLK_ISP 210 271 #define HCLK_ISP 211 272 #define CLK_ISP 212 273 #define PCLK_CSI2HOST1 213 274 #define CLK_CIF_OUT 214 275 #define CLK_CAM0_OUT 215 276 #define CLK_CAM1_OUT 216 277 #define ACLK_VO 217 278 #define HCLK_VO 218 279 #define PCLK_VO 219 280 #define ACLK_VOP_PRE 220 281 #define ACLK_VOP 221 282 #define HCLK_VOP 222 283 #define DCLK_VOP0 223 284 #define DCLK_VOP1 224 285 #define DCLK_VOP2 225 286 #define CLK_VOP_PWM 226 287 #define ACLK_HDCP 227 288 #define HCLK_HDCP 228 289 #define PCLK_HDCP 229 290 #define PCLK_HDMI_HOST 230 291 #define CLK_HDMI_SFR 231 292 #define CLK_HDMI_CEC 231 293 #define PCLK_DSITX_0 232 294 #define PCLK_DSITX_1 233 295 #define PCLK_EDP_CTRL 234 296 #define CLK_EDP_200M 235 297 #define ACLK_VPU_PRE 236 298 #define HCLK_VPU_PRE 237 299 #define ACLK_VPU 238 300 #define HCLK_VPU 239 301 #define ACLK_RGA_PRE 240 302 #define HCLK_RGA_PRE 241 303 #define PCLK_RGA_PRE 242 304 #define ACLK_RGA 243 305 #define HCLK_RGA 244 306 #define CLK_RGA_CORE 245 307 #define ACLK_IEP 246 308 #define HCLK_IEP 247 309 #define CLK_IEP_CORE 248 310 #define HCLK_EBC 249 311 #define DCLK_EBC 250 312 #define ACLK_JDEC 251 313 #define HCLK_JDEC 252 314 #define ACLK_JENC 253 315 #define HCLK_JENC 254 316 #define PCLK_EINK 255 317 #define HCLK_EINK 256 318 #define ACLK_RKVENC_PRE 257 319 #define HCLK_RKVENC_PRE 258 320 #define ACLK_RKVENC 259 321 #define HCLK_RKVENC 260 322 #define CLK_RKVENC_CORE 261 323 #define ACLK_RKVDEC_PRE 262 324 #define HCLK_RKVDEC_PRE 263 325 #define ACLK_RKVDEC 264 326 #define HCLK_RKVDEC 265 327 #define CLK_RKVDEC_CA 266 328 #define CLK_RKVDEC_CORE 267 329 #define CLK_RKVDEC_HEVC_CA 268 330 #define ACLK_BUS 269 331 #define PCLK_BUS 270 332 #define PCLK_TSADC 271 333 #define CLK_TSADC_TSEN 272 334 #define CLK_TSADC 273 335 #define PCLK_SARADC 274 336 #define CLK_SARADC 275 337 #define PCLK_SCR 276 338 #define PCLK_WDT_NS 277 339 #define TCLK_WDT_NS 278 340 #define ACLK_DMAC0 279 341 #define ACLK_DMAC1 280 342 #define ACLK_MCU 281 343 #define PCLK_INTMUX 282 344 #define PCLK_MAILBOX 283 345 #define PCLK_UART1 284 346 #define CLK_UART1_SRC 285 347 #define CLK_UART1_FRAC 286 348 #define SCLK_UART1 287 349 #define PCLK_UART2 288 350 #define CLK_UART2_SRC 289 351 #define CLK_UART2_FRAC 290 352 #define SCLK_UART2 291 353 #define PCLK_UART3 292 354 #define CLK_UART3_SRC 293 355 #define CLK_UART3_FRAC 294 356 #define SCLK_UART3 295 357 #define PCLK_UART4 296 358 #define CLK_UART4_SRC 297 359 #define CLK_UART4_FRAC 298 360 #define SCLK_UART4 299 361 #define PCLK_UART5 300 362 #define CLK_UART5_SRC 301 363 #define CLK_UART5_FRAC 302 364 #define SCLK_UART5 303 365 #define PCLK_UART6 304 366 #define CLK_UART6_SRC 305 367 #define CLK_UART6_FRAC 306 368 #define SCLK_UART6 307 369 #define PCLK_UART7 308 370 #define CLK_UART7_SRC 309 371 #define CLK_UART7_FRAC 310 372 #define SCLK_UART7 311 373 #define PCLK_UART8 312 374 #define CLK_UART8_SRC 313 375 #define CLK_UART8_FRAC 314 376 #define SCLK_UART8 315 377 #define PCLK_UART9 316 378 #define CLK_UART9_SRC 317 379 #define CLK_UART9_FRAC 318 380 #define SCLK_UART9 319 381 #define PCLK_CAN0 320 382 #define CLK_CAN0 321 383 #define PCLK_CAN1 322 384 #define CLK_CAN1 323 385 #define PCLK_CAN2 324 386 #define CLK_CAN2 325 387 #define CLK_I2C 326 388 #define PCLK_I2C1 327 389 #define CLK_I2C1 328 390 #define PCLK_I2C2 329 391 #define CLK_I2C2 330 392 #define PCLK_I2C3 331 393 #define CLK_I2C3 332 394 #define PCLK_I2C4 333 395 #define CLK_I2C4 334 396 #define PCLK_I2C5 335 397 #define CLK_I2C5 336 398 #define PCLK_SPI0 337 399 #define CLK_SPI0 338 400 #define PCLK_SPI1 339 401 #define CLK_SPI1 340 402 #define PCLK_SPI2 341 403 #define CLK_SPI2 342 404 #define PCLK_SPI3 343 405 #define CLK_SPI3 344 406 #define PCLK_PWM1 345 407 #define CLK_PWM1 346 408 #define CLK_PWM1_CAPTURE 347 409 #define PCLK_PWM2 348 410 #define CLK_PWM2 349 411 #define CLK_PWM2_CAPTURE 350 412 #define PCLK_PWM3 351 413 #define CLK_PWM3 352 414 #define CLK_PWM3_CAPTURE 353 415 #define DBCLK_GPIO 354 416 #define PCLK_GPIO1 355 417 #define DBCLK_GPIO1 356 418 #define PCLK_GPIO2 357 419 #define DBCLK_GPIO2 358 420 #define PCLK_GPIO3 359 421 #define DBCLK_GPIO3 360 422 #define PCLK_GPIO4 361 423 #define DBCLK_GPIO4 362 424 #define OCC_SCAN_CLK_GPIO 363 425 #define PCLK_TIMER 364 426 #define CLK_TIMER0 365 427 #define CLK_TIMER1 366 428 #define CLK_TIMER2 367 429 #define CLK_TIMER3 368 430 #define CLK_TIMER4 369 431 #define CLK_TIMER5 370 432 #define ACLK_TOP_HIGH 371 433 #define ACLK_TOP_LOW 372 434 #define HCLK_TOP 373 435 #define PCLK_TOP 374 436 #define PCLK_PCIE30PHY 375 437 #define CLK_OPTC_ARB 376 438 #define PCLK_MIPICSIPHY 377 439 #define PCLK_MIPIDSIPHY0 378 440 #define PCLK_MIPIDSIPHY1 379 441 #define PCLK_PIPEPHY0 380 442 #define PCLK_PIPEPHY1 381 443 #define PCLK_PIPEPHY2 382 444 #define PCLK_CPU_BOOST 383 445 #define CLK_CPU_BOOST 384 446 #define PCLK_OTPPHY 385 447 #define SCLK_GMAC0 386 448 #define SCLK_GMAC0_RGMII_SPEED 387 449 #define SCLK_GMAC0_RMII_SPEED 388 450 #define SCLK_GMAC0_RX_TX 389 451 #define SCLK_GMAC1 390 452 #define SCLK_GMAC1_RGMII_SPEED 391 453 #define SCLK_GMAC1_RMII_SPEED 392 454 #define SCLK_GMAC1_RX_TX 393 455 #define SCLK_SDMMC0_DRV 394 456 #define SCLK_SDMMC0_SAMPLE 395 457 #define SCLK_SDMMC1_DRV 396 458 #define SCLK_SDMMC1_SAMPLE 397 459 #define SCLK_SDMMC2_DRV 398 460 #define SCLK_SDMMC2_SAMPLE 399 461 #define SCLK_EMMC_DRV 400 462 #define SCLK_EMMC_SAMPLE 401 463 #define PCLK_EDPPHY_GRF 402 464 #define PCLK_CORE_PVTM 403 465 466 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) 467 468 /* pmu soft-reset indices */ 469 /* pmucru_softrst_con0 */ 470 #define SRST_P_PDPMU_NIU 0 471 #define SRST_P_PMUCRU 1 472 #define SRST_P_PMUGRF 2 473 #define SRST_P_I2C0 3 474 #define SRST_I2C0 4 475 #define SRST_P_UART0 5 476 #define SRST_S_UART0 6 477 #define SRST_P_PWM0 7 478 #define SRST_PWM0 8 479 #define SRST_P_GPIO0 9 480 #define SRST_GPIO0 10 481 #define SRST_P_PMUPVTM 11 482 #define SRST_PMUPVTM 12 483 484 /* soft-reset indices */ 485 486 /* cru_softrst_con0 */ 487 #define SRST_NCORERESET0 0 488 #define SRST_NCORERESET1 1 489 #define SRST_NCORERESET2 2 490 #define SRST_NCORERESET3 3 491 #define SRST_NCPUPORESET0 4 492 #define SRST_NCPUPORESET1 5 493 #define SRST_NCPUPORESET2 6 494 #define SRST_NCPUPORESET3 7 495 #define SRST_NSRESET 8 496 #define SRST_NSPORESET 9 497 #define SRST_NATRESET 10 498 #define SRST_NGICRESET 11 499 #define SRST_NPRESET 12 500 #define SRST_NPERIPHRESET 13 501 502 /* cru_softrst_con1 */ 503 #define SRST_A_CORE_NIU2DDR 16 504 #define SRST_A_CORE_NIU2BUS 17 505 #define SRST_P_DBG_NIU 18 506 #define SRST_P_DBG 19 507 #define SRST_P_DBG_DAPLITE 20 508 #define SRST_DAP 21 509 #define SRST_A_ADB400_CORE2GIC 22 510 #define SRST_A_ADB400_GIC2CORE 23 511 #define SRST_P_CORE_GRF 24 512 #define SRST_P_CORE_PVTM 25 513 #define SRST_CORE_PVTM 26 514 #define SRST_CORE_PVTPLL 27 515 516 /* cru_softrst_con2 */ 517 #define SRST_GPU 32 518 #define SRST_A_GPU_NIU 33 519 #define SRST_P_GPU_NIU 34 520 #define SRST_P_GPU_PVTM 35 521 #define SRST_GPU_PVTM 36 522 #define SRST_GPU_PVTPLL 37 523 #define SRST_A_NPU_NIU 40 524 #define SRST_H_NPU_NIU 41 525 #define SRST_P_NPU_NIU 42 526 #define SRST_A_NPU 43 527 #define SRST_H_NPU 44 528 #define SRST_P_NPU_PVTM 45 529 #define SRST_NPU_PVTM 46 530 #define SRST_NPU_PVTPLL 47 531 532 /* cru_softrst_con3 */ 533 #define SRST_A_MSCH 51 534 #define SRST_HWFFC_CTRL 52 535 #define SRST_DDR_ALWAYSON 53 536 #define SRST_A_DDRSPLIT 54 537 #define SRST_DDRDFI_CTL 55 538 #define SRST_A_DMA2DDR 57 539 540 /* cru_softrst_con4 */ 541 #define SRST_A_PERIMID_NIU 64 542 #define SRST_H_PERIMID_NIU 65 543 #define SRST_A_GIC_AUDIO_NIU 66 544 #define SRST_H_GIC_AUDIO_NIU 67 545 #define SRST_A_GIC600 68 546 #define SRST_A_GIC600_DEBUG 69 547 #define SRST_A_GICADB_CORE2GIC 70 548 #define SRST_A_GICADB_GIC2CORE 71 549 #define SRST_A_SPINLOCK 72 550 #define SRST_H_SDMMC_BUFFER 73 551 #define SRST_D_SDMMC_BUFFER 74 552 #define SRST_H_I2S0_8CH 75 553 #define SRST_H_I2S1_8CH 76 554 #define SRST_H_I2S2_2CH 77 555 #define SRST_H_I2S3_2CH 78 556 557 /* cru_softrst_con5 */ 558 #define SRST_M_I2S0_8CH_TX 80 559 #define SRST_M_I2S0_8CH_RX 81 560 #define SRST_M_I2S1_8CH_TX 82 561 #define SRST_M_I2S1_8CH_RX 83 562 #define SRST_M_I2S2_2CH 84 563 #define SRST_M_I2S3_2CH_TX 85 564 #define SRST_M_I2S3_2CH_RX 86 565 #define SRST_H_PDM 87 566 #define SRST_M_PDM 88 567 #define SRST_H_VAD 89 568 #define SRST_H_SPDIF_8CH 90 569 #define SRST_M_SPDIF_8CH 91 570 #define SRST_H_AUDPWM 92 571 #define SRST_S_AUDPWM 93 572 #define SRST_H_ACDCDIG 94 573 #define SRST_ACDCDIG 95 574 575 /* cru_softrst_con6 */ 576 #define SRST_A_SECURE_FLASH_NIU 96 577 #define SRST_H_SECURE_FLASH_NIU 97 578 #define SRST_A_CRYPTO_NS 103 579 #define SRST_H_CRYPTO_NS 104 580 #define SRST_CRYPTO_NS_CORE 105 581 #define SRST_CRYPTO_NS_PKA 106 582 #define SRST_CRYPTO_NS_RNG 107 583 #define SRST_H_TRNG_NS 108 584 #define SRST_TRNG_NS 109 585 586 /* cru_softrst_con7 */ 587 #define SRST_H_NANDC 112 588 #define SRST_N_NANDC 113 589 #define SRST_H_SFC 114 590 #define SRST_H_SFC_XIP 115 591 #define SRST_S_SFC 116 592 #define SRST_A_EMMC 117 593 #define SRST_H_EMMC 118 594 #define SRST_B_EMMC 119 595 #define SRST_C_EMMC 120 596 #define SRST_T_EMMC 121 597 598 /* cru_softrst_con8 */ 599 #define SRST_A_PIPE_NIU 128 600 #define SRST_P_PIPE_NIU 130 601 #define SRST_P_PIPE_GRF 133 602 #define SRST_A_SATA0 134 603 #define SRST_SATA0_PIPE 135 604 #define SRST_SATA0_PMALIVE 136 605 #define SRST_SATA0_RXOOB 137 606 #define SRST_A_SATA1 138 607 #define SRST_SATA1_PIPE 139 608 #define SRST_SATA1_PMALIVE 140 609 #define SRST_SATA1_RXOOB 141 610 611 /* cru_softrst_con9 */ 612 #define SRST_A_SATA2 144 613 #define SRST_SATA2_PIPE 145 614 #define SRST_SATA2_PMALIVE 146 615 #define SRST_SATA2_RXOOB 147 616 #define SRST_USB3OTG0 148 617 #define SRST_USB3OTG1 149 618 #define SRST_XPCS 150 619 #define SRST_XPCS_TX_DIV10 151 620 #define SRST_XPCS_RX_DIV10 152 621 #define SRST_XPCS_XGXS_RX 153 622 623 /* cru_softrst_con10 */ 624 #define SRST_P_PCIE20 160 625 626 /* cru_softrst_con11 */ 627 #define SRST_P_PCIE30X1 176 628 629 /* cru_softrst_con12 */ 630 #define SRST_P_PCIE30X2 192 631 632 /* cru_softrst_con13 */ 633 #define SRST_A_PHP_NIU 208 634 #define SRST_H_PHP_NIU 209 635 #define SRST_P_PHP_NIU 210 636 #define SRST_H_SDMMC0 211 637 #define SRST_SDMMC0 212 638 #define SRST_H_SDMMC1 213 639 #define SRST_SDMMC1 214 640 #define SRST_A_GMAC0 215 641 #define SRST_GMAC0_TIMESTAMP 216 642 643 /* cru_softrst_con14 */ 644 #define SRST_A_USB_NIU 224 645 #define SRST_H_USB_NIU 225 646 #define SRST_P_USB_NIU 226 647 #define SRST_P_USB_GRF 227 648 #define SRST_H_USB2HOST0 228 649 #define SRST_H_USB2HOST0_ARB 229 650 #define SRST_USB2HOST0_UTMI 230 651 #define SRST_H_USB2HOST1 231 652 #define SRST_H_USB2HOST1_ARB 232 653 #define SRST_USB2HOST1_UTMI 233 654 #define SRST_H_SDMMC2 234 655 #define SRST_SDMMC2 235 656 #define SRST_A_GMAC1 236 657 #define SRST_GMAC1_TIMESTAMP 237 658 659 /* cru_softrst_con15 */ 660 #define SRST_A_VI_NIU 240 661 #define SRST_H_VI_NIU 241 662 #define SRST_P_VI_NIU 242 663 #define SRST_A_VICAP 247 664 #define SRST_H_VICAP 248 665 #define SRST_D_VICAP 249 666 #define SRST_I_VICAP 250 667 #define SRST_P_VICAP 251 668 #define SRST_H_ISP 252 669 #define SRST_ISP 253 670 #define SRST_P_CSI2HOST1 255 671 672 /* cru_softrst_con16 */ 673 #define SRST_A_VO_NIU 256 674 #define SRST_H_VO_NIU 257 675 #define SRST_P_VO_NIU 258 676 #define SRST_A_VOP_NIU 259 677 #define SRST_A_VOP 260 678 #define SRST_H_VOP 261 679 #define SRST_VOP0 262 680 #define SRST_VOP1 263 681 #define SRST_VOP2 264 682 #define SRST_VOP_PWM 265 683 #define SRST_A_HDCP 266 684 #define SRST_H_HDCP 267 685 #define SRST_P_HDCP 268 686 #define SRST_P_HDMI_HOST 270 687 #define SRST_HDMI_HOST 271 688 689 /* cru_softrst_con17 */ 690 #define SRST_P_DSITX_0 272 691 #define SRST_P_DSITX_1 273 692 #define SRST_P_EDP_CTRL 274 693 #define SRST_EDP_24M 275 694 #define SRST_A_VPU_NIU 280 695 #define SRST_H_VPU_NIU 281 696 #define SRST_A_VPU 282 697 #define SRST_H_VPU 283 698 #define SRST_H_EINK 286 699 #define SRST_P_EINK 287 700 701 /* cru_softrst_con18 */ 702 #define SRST_A_RGA_NIU 288 703 #define SRST_H_RGA_NIU 289 704 #define SRST_P_RGA_NIU 290 705 #define SRST_A_RGA 292 706 #define SRST_H_RGA 293 707 #define SRST_RGA_CORE 294 708 #define SRST_A_IEP 295 709 #define SRST_H_IEP 296 710 #define SRST_IEP_CORE 297 711 #define SRST_H_EBC 298 712 #define SRST_D_EBC 299 713 #define SRST_A_JDEC 300 714 #define SRST_H_JDEC 301 715 #define SRST_A_JENC 302 716 #define SRST_H_JENC 303 717 718 /* cru_softrst_con19 */ 719 #define SRST_A_VENC_NIU 304 720 #define SRST_H_VENC_NIU 305 721 #define SRST_A_RKVENC 307 722 #define SRST_H_RKVENC 308 723 #define SRST_RKVENC_CORE 309 724 725 /* cru_softrst_con20 */ 726 #define SRST_A_RKVDEC_NIU 320 727 #define SRST_H_RKVDEC_NIU 321 728 #define SRST_A_RKVDEC 322 729 #define SRST_H_RKVDEC 323 730 #define SRST_RKVDEC_CA 324 731 #define SRST_RKVDEC_CORE 325 732 #define SRST_RKVDEC_HEVC_CA 326 733 734 /* cru_softrst_con21 */ 735 #define SRST_A_BUS_NIU 336 736 #define SRST_P_BUS_NIU 338 737 #define SRST_P_CAN0 340 738 #define SRST_CAN0 341 739 #define SRST_P_CAN1 342 740 #define SRST_CAN1 343 741 #define SRST_P_CAN2 344 742 #define SRST_CAN2 345 743 #define SRST_P_GPIO1 346 744 #define SRST_GPIO1 347 745 #define SRST_P_GPIO2 348 746 #define SRST_GPIO2 349 747 #define SRST_P_GPIO3 350 748 #define SRST_GPIO3 351 749 750 /* cru_softrst_con22 */ 751 #define SRST_P_GPIO4 352 752 #define SRST_GPIO4 353 753 #define SRST_P_I2C1 354 754 #define SRST_I2C1 355 755 #define SRST_P_I2C2 356 756 #define SRST_I2C2 357 757 #define SRST_P_I2C3 358 758 #define SRST_I2C3 359 759 #define SRST_P_I2C4 360 760 #define SRST_I2C4 361 761 #define SRST_P_I2C5 362 762 #define SRST_I2C5 363 763 #define SRST_P_OTPC_NS 364 764 #define SRST_OTPC_NS_SBPI 365 765 #define SRST_OTPC_NS_USR 366 766 767 /* cru_softrst_con23 */ 768 #define SRST_P_PWM1 368 769 #define SRST_PWM1 369 770 #define SRST_P_PWM2 370 771 #define SRST_PWM2 371 772 #define SRST_P_PWM3 372 773 #define SRST_PWM3 373 774 #define SRST_P_SPI0 374 775 #define SRST_SPI0 375 776 #define SRST_P_SPI1 376 777 #define SRST_SPI1 377 778 #define SRST_P_SPI2 378 779 #define SRST_SPI2 379 780 #define SRST_P_SPI3 380 781 #define SRST_SPI3 381 782 783 /* cru_softrst_con24 */ 784 #define SRST_P_SARADC 384 785 #define SRST_P_TSADC 385 786 #define SRST_TSADC 386 787 #define SRST_P_TIMER 387 788 #define SRST_TIMER0 388 789 #define SRST_TIMER1 389 790 #define SRST_TIMER2 390 791 #define SRST_TIMER3 391 792 #define SRST_TIMER4 392 793 #define SRST_TIMER5 393 794 #define SRST_P_UART1 394 795 #define SRST_S_UART1 395 796 797 /* cru_softrst_con25 */ 798 #define SRST_P_UART2 400 799 #define SRST_S_UART2 401 800 #define SRST_P_UART3 402 801 #define SRST_S_UART3 403 802 #define SRST_P_UART4 404 803 #define SRST_S_UART4 405 804 #define SRST_P_UART5 406 805 #define SRST_S_UART5 407 806 #define SRST_P_UART6 408 807 #define SRST_S_UART6 409 808 #define SRST_P_UART7 410 809 #define SRST_S_UART7 411 810 #define SRST_P_UART8 412 811 #define SRST_S_UART8 413 812 #define SRST_P_UART9 414 813 #define SRST_S_UART9 415 814 815 /* cru_softrst_con26 */ 816 #define SRST_P_GRF 416 817 #define SRST_P_GRF_VCCIO12 417 818 #define SRST_P_GRF_VCCIO34 418 819 #define SRST_P_GRF_VCCIO567 419 820 #define SRST_P_SCR 420 821 #define SRST_P_WDT_NS 421 822 #define SRST_T_WDT_NS 422 823 #define SRST_P_DFT2APB 423 824 #define SRST_A_MCU 426 825 #define SRST_P_INTMUX 427 826 #define SRST_P_MAILBOX 428 827 828 /* cru_softrst_con27 */ 829 #define SRST_A_TOP_HIGH_NIU 432 830 #define SRST_A_TOP_LOW_NIU 433 831 #define SRST_H_TOP_NIU 434 832 #define SRST_P_TOP_NIU 435 833 #define SRST_P_TOP_CRU 438 834 #define SRST_P_DDRPHY 439 835 #define SRST_DDRPHY 440 836 #define SRST_P_MIPICSIPHY 442 837 #define SRST_P_MIPIDSIPHY0 443 838 #define SRST_P_MIPIDSIPHY1 444 839 #define SRST_P_PCIE30PHY 445 840 #define SRST_PCIE30PHY 446 841 #define SRST_P_PCIE30PHY_GRF 447 842 843 /* cru_softrst_con28 */ 844 #define SRST_P_APB2ASB_LEFT 448 845 #define SRST_P_APB2ASB_BOTTOM 449 846 #define SRST_P_ASB2APB_LEFT 450 847 #define SRST_P_ASB2APB_BOTTOM 451 848 #define SRST_P_PIPEPHY0 452 849 #define SRST_PIPEPHY0 453 850 #define SRST_P_PIPEPHY1 454 851 #define SRST_PIPEPHY1 455 852 #define SRST_P_PIPEPHY2 456 853 #define SRST_PIPEPHY2 457 854 #define SRST_P_USB2PHY0_GRF 458 855 #define SRST_P_USB2PHY1_GRF 459 856 #define SRST_P_CPU_BOOST 460 857 #define SRST_CPU_BOOST 461 858 #define SRST_P_OTPPHY 462 859 #define SRST_OTPPHY 463 860 861 /* cru_softrst_con29 */ 862 #define SRST_USB2PHY0_POR 464 863 #define SRST_USB2PHY0_USB3OTG0 465 864 #define SRST_USB2PHY0_USB3OTG1 466 865 #define SRST_USB2PHY1_POR 467 866 #define SRST_USB2PHY1_USB2HOST0 468 867 #define SRST_USB2PHY1_USB2HOST1 469 868 #define SRST_P_EDPPHY_GRF 470 869 #define SRST_TSADCPHY 471 870 #define SRST_GMAC0_DELAYLINE 472 871 #define SRST_GMAC1_DELAYLINE 473 872 #define SRST_OTPC_ARB 474 873 #define SRST_P_PIPEPHY0_GRF 475 874 #define SRST_P_PIPEPHY1_GRF 476 875 #define SRST_P_PIPEPHY2_GRF 477 876 877 #endif 878