1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 3 * Author: Finley Xiao <finley.xiao@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H 18 19 /* core clocks */ 20 #define PLL_APLL 1 21 #define PLL_DPLL 2 22 #define PLL_VPLL0 3 23 #define PLL_VPLL1 4 24 #define ARMCLK 5 25 26 /* sclk (special clocks) */ 27 #define USB480M 14 28 #define SCLK_RTC32K 15 29 #define SCLK_PVTM_CORE 16 30 #define SCLK_UART0 17 31 #define SCLK_UART1 18 32 #define SCLK_UART2 19 33 #define SCLK_UART3 20 34 #define SCLK_UART4 21 35 #define SCLK_I2C0 22 36 #define SCLK_I2C1 23 37 #define SCLK_I2C2 24 38 #define SCLK_I2C3 25 39 #define SCLK_PWM 26 40 #define SCLK_SPI0 27 41 #define SCLK_SPI1 28 42 #define SCLK_SPI2 29 43 #define SCLK_TIMER0 30 44 #define SCLK_TIMER1 31 45 #define SCLK_TIMER2 32 46 #define SCLK_TIMER3 33 47 #define SCLK_TIMER4 34 48 #define SCLK_TIMER5 35 49 #define SCLK_TSADC 36 50 #define SCLK_SARADC 37 51 #define SCLK_OTP 38 52 #define SCLK_OTP_USR 39 53 #define SCLK_CPU_BOOST 40 54 #define SCLK_CRYPTO 41 55 #define SCLK_CRYPTO_APK 42 56 #define SCLK_NANDC_DIV 43 57 #define SCLK_NANDC_DIV50 44 58 #define SCLK_NANDC 45 59 #define SCLK_SDMMC_DIV 46 60 #define SCLK_SDMMC_DIV50 47 61 #define SCLK_SDMMC 48 62 #define SCLK_SDMMC_DRV 49 63 #define SCLK_SDMMC_SAMPLE 50 64 #define SCLK_SDIO_DIV 51 65 #define SCLK_SDIO_DIV50 52 66 #define SCLK_SDIO 53 67 #define SCLK_SDIO_DRV 54 68 #define SCLK_SDIO_SAMPLE 55 69 #define SCLK_EMMC_DIV 56 70 #define SCLK_EMMC_DIV50 57 71 #define SCLK_EMMC 58 72 #define SCLK_EMMC_DRV 59 73 #define SCLK_EMMC_SAMPLE 60 74 #define SCLK_SFC 61 75 #define SCLK_OTG_ADP 62 76 #define SCLK_GMAC_SRC 63 77 #define SCLK_GMAC 64 78 #define SCLK_MAC_REF 65 79 #define SCLK_GMAC_RX_TX 66 80 #define SCLK_GMAC_RMII 67 81 #define SCLK_DDR_MON_TIMER 68 82 #define SCLK_DDR_MON 69 83 #define SCLK_DDRCLK 70 84 #define SCLK_PMU 71 85 #define SCLK_USBPHY_REF 72 86 #define SCLK_WIFI 73 87 #define SCLK_PVTM_PMU 74 88 #define SCLK_PDM 75 89 #define SCLK_I2S0_8CH_TX 76 90 #define SCLK_I2S0_8CH_TX_OUT 77 91 #define SCLK_I2S0_8CH_RX 78 92 #define SCLK_I2S0_8CH_RX_OUT 79 93 #define SCLK_I2S1_8CH_TX 80 94 #define SCLK_I2S1_8CH_TX_OUT 81 95 #define SCLK_I2S1_8CH_RX 82 96 #define SCLK_I2S1_8CH_RX_OUT 83 97 #define SCLK_I2S2_8CH_TX 84 98 #define SCLK_I2S2_8CH_TX_OUT 85 99 #define SCLK_I2S2_8CH_RX 86 100 #define SCLK_I2S2_8CH_RX_OUT 87 101 #define SCLK_I2S3_8CH_TX 88 102 #define SCLK_I2S3_8CH_TX_OUT 89 103 #define SCLK_I2S3_8CH_RX 90 104 #define SCLK_I2S3_8CH_RX_OUT 91 105 #define SCLK_I2S0_2CH 92 106 #define SCLK_I2S0_2CH_OUT 93 107 #define SCLK_I2S1_2CH 94 108 #define SCLK_I2S1_2CH_OUT 95 109 #define SCLK_SPDIF_TX_DIV 96 110 #define SCLK_SPDIF_TX_DIV50 97 111 #define SCLK_SPDIF_TX 98 112 #define SCLK_SPDIF_RX_DIV 99 113 #define SCLK_SPDIF_RX_DIV50 100 114 #define SCLK_SPDIF_RX 101 115 116 /* dclk */ 117 #define DCLK_VOP 120 118 119 /* aclk */ 120 #define ACLK_CORE 130 121 #define ACLK_BUS 131 122 #define ACLK_PERI 132 123 #define ACLK_GMAC 133 124 #define ACLK_CRYPTO 134 125 #define ACLK_VOP 135 126 #define ACLK_GIC 136 127 128 /* hclk */ 129 #define HCLK_BUS 150 130 #define HCLK_PERI 151 131 #define HCLK_AUDIO 152 132 #define HCLK_NANDC 153 133 #define HCLK_SDMMC 154 134 #define HCLK_SDIO 155 135 #define HCLK_EMMC 156 136 #define HCLK_SFC 157 137 #define HCLK_OTG 158 138 #define HCLK_HOST 159 139 #define HCLK_HOST_ARB 160 140 #define HCLK_PDM 161 141 #define HCLK_SPDIFTX 162 142 #define HCLK_SPDIFRX 163 143 #define HCLK_I2S0_8CH 164 144 #define HCLK_I2S1_8CH 165 145 #define HCLK_I2S2_8CH 166 146 #define HCLK_I2S3_8CH 167 147 #define HCLK_I2S0_2CH 168 148 #define HCLK_I2S1_2CH 169 149 #define HCLK_VAD 170 150 #define HCLK_CRYPTO 171 151 #define HCLK_VOP 172 152 153 /* pclk */ 154 #define PCLK_BUS 190 155 #define PCLK_DDR 191 156 #define PCLK_PERI 192 157 #define PCLK_PMU 193 158 #define PCLK_AUDIO 194 159 #define PCLK_GMAC 195 160 #define PCLK_ACODEC 196 161 #define PCLK_UART0 197 162 #define PCLK_UART1 198 163 #define PCLK_UART2 199 164 #define PCLK_UART3 200 165 #define PCLK_UART4 201 166 #define PCLK_I2C0 202 167 #define PCLK_I2C1 203 168 #define PCLK_I2C2 204 169 #define PCLK_I2C3 205 170 #define PCLK_PWM 206 171 #define PCLK_SPI0 207 172 #define PCLK_SPI1 208 173 #define PCLK_SPI2 209 174 #define PCLK_SARADC 210 175 #define PCLK_TSADC 211 176 #define PCLK_TIMER 212 177 #define PCLK_OTP_NS 213 178 #define PCLK_WDT_NS 214 179 #define PCLK_GPIO0 215 180 #define PCLK_GPIO1 216 181 #define PCLK_GPIO2 217 182 #define PCLK_GPIO3 218 183 #define PCLK_GPIO4 219 184 #define PCLK_SGRF 220 185 #define PCLK_GRF 221 186 #define PCLK_USBSD_DET 222 187 #define PCLK_DDR_UPCTL 223 188 #define PCLK_DDR_MON 224 189 #define PCLK_DDRPHY 225 190 #define PCLK_DDR_STDBY 226 191 #define PCLK_USB_GRF 227 192 #define PCLK_CRU 228 193 #define PCLK_OTP_PHY 229 194 #define PCLK_CPU_BOOST 230 195 196 #define CLK_NR_CLKS (PCLK_CPU_BOOST + 1) 197 198 /* soft-reset indices */ 199 200 /* cru_softrst_con0 */ 201 #define SRST_CORE0_PO 0 202 #define SRST_CORE1_PO 1 203 #define SRST_CORE2_PO 2 204 #define SRST_CORE3_PO 3 205 #define SRST_CORE0 4 206 #define SRST_CORE1 5 207 #define SRST_CORE2 6 208 #define SRST_CORE3 7 209 #define SRST_CORE0_DBG 8 210 #define SRST_CORE1_DBG 9 211 #define SRST_CORE2_DBG 10 212 #define SRST_CORE3_DBG 11 213 #define SRST_TOPDBG 12 214 #define SRST_CORE_NOC 13 215 #define SRST_STRC_A 14 216 #define SRST_L2C 15 217 218 /* cru_softrst_con1 */ 219 #define SRST_DAP 16 220 #define SRST_CORE_PVTM 17 221 #define SRST_CORE_PRF 18 222 #define SRST_CORE_GRF 19 223 #define SRST_DDRUPCTL 20 224 #define SRST_DDRUPCTL_P 22 225 #define SRST_MSCH 23 226 #define SRST_DDRMON_P 25 227 #define SRST_DDRSTDBY_P 26 228 #define SRST_DDRSTDBY 27 229 #define SRST_DDRPHY 28 230 #define SRST_DDRPHY_DIV 29 231 #define SRST_DDRPHY_P 30 232 233 /* cru_softrst_con2 */ 234 #define SRST_BUS_NIU_H 32 235 #define SRST_USB_NIU_P 33 236 #define SRST_CRYPTO_A 34 237 #define SRST_CRYPTO_H 35 238 #define SRST_CRYPTO 36 239 #define SRST_CRYPTO_APK 37 240 #define SRST_VOP_A 38 241 #define SRST_VOP_H 39 242 #define SRST_VOP_D 40 243 #define SRST_INTMEM_A 41 244 #define SRST_ROM_H 42 245 #define SRST_GIC_A 43 246 #define SRST_UART0_P 44 247 #define SRST_UART0 45 248 #define SRST_UART1_P 46 249 #define SRST_UART1 47 250 251 /* cru_softrst_con3 */ 252 #define SRST_UART2_P 48 253 #define SRST_UART2 49 254 #define SRST_UART3_P 50 255 #define SRST_UART3 51 256 #define SRST_UART4_P 52 257 #define SRST_UART4 53 258 #define SRST_I2C0_P 54 259 #define SRST_I2C0 55 260 #define SRST_I2C1_P 56 261 #define SRST_I2C1 57 262 #define SRST_I2C2_P 58 263 #define SRST_I2C2 59 264 #define SRST_I2C3_P 60 265 #define SRST_I2C3 61 266 #define SRST_PWM_P 62 267 #define SRST_PWM 63 268 269 /* cru_softrst_con4 */ 270 #define SRST_SPI0_P 64 271 #define SRST_SPI0 65 272 #define SRST_SPI1_P 66 273 #define SRST_SPI1 67 274 #define SRST_SPI2_P 68 275 #define SRST_SPI2 69 276 #define SRST_SARADC_P 70 277 #define SRST_TSADC_P 71 278 #define SRST_TSADC 72 279 #define SRST_TIMER0_P 73 280 #define SRST_TIMER0 74 281 #define SRST_TIMER1 75 282 #define SRST_TIMER2 76 283 #define SRST_TIMER3 77 284 #define SRST_TIMER4 78 285 #define SRST_TIMER5 79 286 287 /* cru_softrst_con5 */ 288 #define SRST_OTP_NS_P 80 289 #define SRST_OTP_NS_SBPI 81 290 #define SRST_OTP_NS_USR 82 291 #define SRST_OTP_PHY_P 83 292 #define SRST_OTP_PHY 84 293 #define SRST_GPIO0_P 86 294 #define SRST_GPIO1_P 87 295 #define SRST_GPIO2_P 88 296 #define SRST_GPIO3_P 89 297 #define SRST_GPIO4_P 90 298 #define SRST_GRF_P 91 299 #define SRST_USBSD_DET_P 92 300 #define SRST_PMU 93 301 #define SRST_PMU_PVTM 94 302 #define SRST_USB_GRF_P 95 303 304 /* cru_softrst_con6 */ 305 #define SRST_CPU_BOOST 96 306 #define SRST_CPU_BOOST_P 97 307 #define SRST_PERI_NIU_A 104 308 #define SRST_PERI_NIU_H 105 309 #define SRST_PERI_NIU_p 106 310 #define SRST_USB2OTG_H 107 311 #define SRST_USB2OTG 108 312 #define SRST_USB2OTG_ADP 109 313 #define SRST_USB2HOST_H 110 314 #define SRST_USB2HOST_ARB_H 111 315 316 /* cru_softrst_con7 */ 317 #define SRST_USB2HOST_AUX_H 112 318 #define SRST_USB2HOST_EHCI 113 319 #define SRST_USB2HOST 114 320 #define SRST_USBPHYPOR 115 321 #define SRST_UTMI0 116 322 #define SRST_UTMI1 117 323 #define SRST_SDIO_H 118 324 #define SRST_EMMC_H 119 325 #define SRST_SFC_H 120 326 #define SRST_SFC 121 327 #define SRST_SD_H 122 328 #define SRST_NANDC_H 123 329 #define SRST_NANDC_N 124 330 #define SRST_GMAC_A 125 331 332 /* cru_softrst_con8 */ 333 #define SRST_AUDIO_NIU_H 128 334 #define SRST_AUDIO_NIU_P 129 335 #define SRST_PDM_H 130 336 #define SRST_PDM_M 131 337 #define SRST_SPDIFTX_H 132 338 #define SRST_SPDIFTX_M 133 339 #define SRST_SPDIFRX_H 134 340 #define SRST_SPDIFRX_M 135 341 #define SRST_I2S0_8CH_H 136 342 #define SRST_I2S0_8CH_TX_M 137 343 #define SRST_I2S0_8CH_RX_M 138 344 #define SRST_I2S1_8CH_H 139 345 #define SRST_I2S1_8CH_TX_M 140 346 #define SRST_I2S1_8CH_RX_M 141 347 #define SRST_I2S2_8CH_H 142 348 #define SRST_I2S2_8CH_TX_M 143 349 350 /* cru_softrst_con9 */ 351 #define SRST_I2S2_8CH_RX_M 144 352 #define SRST_I2S3_8CH_H 145 353 #define SRST_I2S3_8CH_TX_M 146 354 #define SRST_I2S3_8CH_RX_M 147 355 #define SRST_I2S0_2CH_H 148 356 #define SRST_I2S0_2CH_M 149 357 #define SRST_I2S1_2CH_H 150 358 #define SRST_I2S1_2CH_M 151 359 #define SRST_VAD_H 152 360 #define SRST_ACODEC_P 153 361 362 #endif 363