1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* core clocks */ 9 #define PLL_APLL 1 10 #define PLL_DPLL 2 11 #define PLL_CPLL 3 12 #define PLL_GPLL 4 13 #define PLL_NPLL 5 14 #define ARMCLK 6 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_GPU 64 18 #define SCLK_SPI0 65 19 #define SCLK_SPI1 66 20 #define SCLK_SPI2 67 21 #define SCLK_SDMMC 68 22 #define SCLK_SDIO0 69 23 #define SCLK_SDIO1 70 24 #define SCLK_EMMC 71 25 #define SCLK_TSADC 72 26 #define SCLK_SARADC 73 27 #define SCLK_PS2C 74 28 #define SCLK_NANDC0 75 29 #define SCLK_NANDC1 76 30 #define SCLK_UART0 77 31 #define SCLK_UART1 78 32 #define SCLK_UART2 79 33 #define SCLK_UART3 80 34 #define SCLK_UART4 81 35 #define SCLK_I2S0 82 36 #define SCLK_SPDIF 83 37 #define SCLK_SPDIF8CH 84 38 #define SCLK_TIMER0 85 39 #define SCLK_TIMER1 86 40 #define SCLK_TIMER2 87 41 #define SCLK_TIMER3 88 42 #define SCLK_TIMER4 89 43 #define SCLK_TIMER5 90 44 #define SCLK_TIMER6 91 45 #define SCLK_HSADC 92 46 #define SCLK_OTGPHY0 93 47 #define SCLK_OTGPHY1 94 48 #define SCLK_OTGPHY2 95 49 #define SCLK_OTG_ADP 96 50 #define SCLK_HSICPHY480M 97 51 #define SCLK_HSICPHY12M 98 52 #define SCLK_MACREF 99 53 #define SCLK_LCDC_PWM0 100 54 #define SCLK_LCDC_PWM1 101 55 #define SCLK_MAC_RX 102 56 #define SCLK_MAC_TX 103 57 #define SCLK_EDP_24M 104 58 #define SCLK_EDP 105 59 #define SCLK_RGA 106 60 #define SCLK_ISP 107 61 #define SCLK_ISP_JPE 108 62 #define SCLK_HDMI_HDCP 109 63 #define SCLK_HDMI_CEC 110 64 #define SCLK_HEVC_CABAC 111 65 #define SCLK_HEVC_CORE 112 66 #define SCLK_I2S0_OUT 113 67 #define SCLK_SDMMC_DRV 114 68 #define SCLK_SDIO0_DRV 115 69 #define SCLK_SDIO1_DRV 116 70 #define SCLK_EMMC_DRV 117 71 #define SCLK_SDMMC_SAMPLE 118 72 #define SCLK_SDIO0_SAMPLE 119 73 #define SCLK_SDIO1_SAMPLE 120 74 #define SCLK_EMMC_SAMPLE 121 75 #define SCLK_USBPHY480M_SRC 122 76 #define SCLK_PVTM_CORE 123 77 #define SCLK_PVTM_GPU 124 78 #define SCLK_MIPIDSI_24M 126 79 80 #define SCLK_MAC_PLL 150 81 #define SCLK_MAC 151 82 #define SCLK_MACREF_OUT 152 83 84 #define DCLK_VOP0 190 85 #define DCLK_VOP1 191 86 87 /* aclk gates */ 88 #define ACLK_GPU 192 89 #define ACLK_DMAC1 193 90 #define ACLK_DMAC2 194 91 #define ACLK_MMU 195 92 #define ACLK_GMAC 196 93 #define ACLK_VOP0 197 94 #define ACLK_VOP1 198 95 #define ACLK_CRYPTO 199 96 #define ACLK_RGA 200 97 #define ACLK_RGA_NIU 201 98 #define ACLK_IEP 202 99 #define ACLK_VIO0_NIU 203 100 #define ACLK_VIP 204 101 #define ACLK_ISP 205 102 #define ACLK_VIO1_NIU 206 103 #define ACLK_HEVC 207 104 #define ACLK_VCODEC 208 105 #define ACLK_CPU 209 106 #define ACLK_PERI 210 107 108 /* pclk gates */ 109 #define PCLK_GPIO0 320 110 #define PCLK_GPIO1 321 111 #define PCLK_GPIO2 322 112 #define PCLK_GPIO3 323 113 #define PCLK_GPIO4 324 114 #define PCLK_GPIO5 325 115 #define PCLK_GPIO6 326 116 #define PCLK_GPIO7 327 117 #define PCLK_GPIO8 328 118 #define PCLK_GRF 329 119 #define PCLK_SGRF 330 120 #define PCLK_PMU 331 121 #define PCLK_I2C0 332 122 #define PCLK_I2C1 333 123 #define PCLK_I2C2 334 124 #define PCLK_I2C3 335 125 #define PCLK_I2C4 336 126 #define PCLK_I2C5 337 127 #define PCLK_SPI0 338 128 #define PCLK_SPI1 339 129 #define PCLK_SPI2 340 130 #define PCLK_UART0 341 131 #define PCLK_UART1 342 132 #define PCLK_UART2 343 133 #define PCLK_UART3 344 134 #define PCLK_UART4 345 135 #define PCLK_TSADC 346 136 #define PCLK_SARADC 347 137 #define PCLK_SIM 348 138 #define PCLK_GMAC 349 139 #define PCLK_PWM 350 140 #define PCLK_RKPWM 351 141 #define PCLK_PS2C 352 142 #define PCLK_TIMER 353 143 #define PCLK_TZPC 354 144 #define PCLK_EDP_CTRL 355 145 #define PCLK_MIPI_DSI0 356 146 #define PCLK_MIPI_DSI1 357 147 #define PCLK_MIPI_CSI 358 148 #define PCLK_LVDS_PHY 359 149 #define PCLK_HDMI_CTRL 360 150 #define PCLK_VIO2_H2P 361 151 #define PCLK_CPU 362 152 #define PCLK_PERI 363 153 #define PCLK_DDRUPCTL0 364 154 #define PCLK_PUBL0 365 155 #define PCLK_DDRUPCTL1 366 156 #define PCLK_PUBL1 367 157 #define PCLK_WDT 368 158 159 /* hclk gates */ 160 #define HCLK_GPS 448 161 #define HCLK_OTG0 449 162 #define HCLK_USBHOST0 450 163 #define HCLK_USBHOST1 451 164 #define HCLK_HSIC 452 165 #define HCLK_NANDC0 453 166 #define HCLK_NANDC1 454 167 #define HCLK_TSP 455 168 #define HCLK_SDMMC 456 169 #define HCLK_SDIO0 457 170 #define HCLK_SDIO1 458 171 #define HCLK_EMMC 459 172 #define HCLK_HSADC 460 173 #define HCLK_CRYPTO 461 174 #define HCLK_I2S0 462 175 #define HCLK_SPDIF 463 176 #define HCLK_SPDIF8CH 464 177 #define HCLK_VOP0 465 178 #define HCLK_VOP1 466 179 #define HCLK_ROM 467 180 #define HCLK_IEP 468 181 #define HCLK_ISP 469 182 #define HCLK_RGA 470 183 #define HCLK_VIO_AHB_ARBI 471 184 #define HCLK_VIO_NIU 472 185 #define HCLK_VIP 473 186 #define HCLK_VIO2_H2P 474 187 #define HCLK_HEVC 475 188 #define HCLK_VCODEC 476 189 #define HCLK_CPU 477 190 #define HCLK_PERI 478 191 192 #define CLK_NR_CLKS (HCLK_PERI + 1) 193 194 /* soft-reset indices */ 195 #define SRST_CORE0 0 196 #define SRST_CORE1 1 197 #define SRST_CORE2 2 198 #define SRST_CORE3 3 199 #define SRST_CORE0_PO 4 200 #define SRST_CORE1_PO 5 201 #define SRST_CORE2_PO 6 202 #define SRST_CORE3_PO 7 203 #define SRST_PDCORE_STRSYS 8 204 #define SRST_PDBUS_STRSYS 9 205 #define SRST_L2C 10 206 #define SRST_TOPDBG 11 207 #define SRST_CORE0_DBG 12 208 #define SRST_CORE1_DBG 13 209 #define SRST_CORE2_DBG 14 210 #define SRST_CORE3_DBG 15 211 212 #define SRST_PDBUG_AHB_ARBITOR 16 213 #define SRST_EFUSE256 17 214 #define SRST_DMAC1 18 215 #define SRST_INTMEM 19 216 #define SRST_ROM 20 217 #define SRST_SPDIF8CH 21 218 #define SRST_TIMER 22 219 #define SRST_I2S0 23 220 #define SRST_SPDIF 24 221 #define SRST_TIMER0 25 222 #define SRST_TIMER1 26 223 #define SRST_TIMER2 27 224 #define SRST_TIMER3 28 225 #define SRST_TIMER4 29 226 #define SRST_TIMER5 30 227 #define SRST_EFUSE 31 228 229 #define SRST_GPIO0 32 230 #define SRST_GPIO1 33 231 #define SRST_GPIO2 34 232 #define SRST_GPIO3 35 233 #define SRST_GPIO4 36 234 #define SRST_GPIO5 37 235 #define SRST_GPIO6 38 236 #define SRST_GPIO7 39 237 #define SRST_GPIO8 40 238 #define SRST_I2C0 42 239 #define SRST_I2C1 43 240 #define SRST_I2C2 44 241 #define SRST_I2C3 45 242 #define SRST_I2C4 46 243 #define SRST_I2C5 47 244 245 #define SRST_DWPWM 48 246 #define SRST_MMC_PERI 49 247 #define SRST_PERIPH_MMU 50 248 #define SRST_DAP 51 249 #define SRST_DAP_SYS 52 250 #define SRST_TPIU 53 251 #define SRST_PMU_APB 54 252 #define SRST_GRF 55 253 #define SRST_PMU 56 254 #define SRST_PERIPH_AXI 57 255 #define SRST_PERIPH_AHB 58 256 #define SRST_PERIPH_APB 59 257 #define SRST_PERIPH_NIU 60 258 #define SRST_PDPERI_AHB_ARBI 61 259 #define SRST_EMEM 62 260 #define SRST_USB_PERI 63 261 262 #define SRST_DMAC2 64 263 #define SRST_MAC 66 264 #define SRST_GPS 67 265 #define SRST_RKPWM 69 266 #define SRST_CCP 71 267 #define SRST_USBHOST0 72 268 #define SRST_HSIC 73 269 #define SRST_HSIC_AUX 74 270 #define SRST_HSIC_PHY 75 271 #define SRST_HSADC 76 272 #define SRST_NANDC0 77 273 #define SRST_NANDC1 78 274 275 #define SRST_TZPC 80 276 #define SRST_SPI0 83 277 #define SRST_SPI1 84 278 #define SRST_SPI2 85 279 #define SRST_SARADC 87 280 #define SRST_PDALIVE_NIU 88 281 #define SRST_PDPMU_INTMEM 89 282 #define SRST_PDPMU_NIU 90 283 #define SRST_SGRF 91 284 285 #define SRST_VIO_ARBI 96 286 #define SRST_RGA_NIU 97 287 #define SRST_VIO0_NIU_AXI 98 288 #define SRST_VIO_NIU_AHB 99 289 #define SRST_LCDC0_AXI 100 290 #define SRST_LCDC0_AHB 101 291 #define SRST_LCDC0_DCLK 102 292 #define SRST_VIO1_NIU_AXI 103 293 #define SRST_VIP 104 294 #define SRST_RGA_CORE 105 295 #define SRST_IEP_AXI 106 296 #define SRST_IEP_AHB 107 297 #define SRST_RGA_AXI 108 298 #define SRST_RGA_AHB 109 299 #define SRST_ISP 110 300 #define SRST_EDP 111 301 302 #define SRST_VCODEC_AXI 112 303 #define SRST_VCODEC_AHB 113 304 #define SRST_VIO_H2P 114 305 #define SRST_MIPIDSI0 115 306 #define SRST_MIPIDSI1 116 307 #define SRST_MIPICSI 117 308 #define SRST_LVDS_PHY 118 309 #define SRST_LVDS_CON 119 310 #define SRST_GPU 120 311 #define SRST_HDMI 121 312 #define SRST_CORE_PVTM 124 313 #define SRST_GPU_PVTM 125 314 315 #define SRST_MMC0 128 316 #define SRST_SDIO0 129 317 #define SRST_SDIO1 130 318 #define SRST_EMMC 131 319 #define SRST_USBOTG_AHB 132 320 #define SRST_USBOTG_PHY 133 321 #define SRST_USBOTG_CON 134 322 #define SRST_USBHOST0_AHB 135 323 #define SRST_USBHOST0_PHY 136 324 #define SRST_USBHOST0_CON 137 325 #define SRST_USBHOST1_AHB 138 326 #define SRST_USBHOST1_PHY 139 327 #define SRST_USBHOST1_CON 140 328 #define SRST_USB_ADP 141 329 #define SRST_ACC_EFUSE 142 330 331 #define SRST_CORESIGHT 144 332 #define SRST_PD_CORE_AHB_NOC 145 333 #define SRST_PD_CORE_APB_NOC 146 334 #define SRST_PD_CORE_MP_AXI 147 335 #define SRST_GIC 148 336 #define SRST_LCDC_PWM0 149 337 #define SRST_LCDC_PWM1 150 338 #define SRST_VIO0_H2P_BRG 151 339 #define SRST_VIO1_H2P_BRG 152 340 #define SRST_RGA_H2P_BRG 153 341 #define SRST_HEVC 154 342 #define SRST_TSADC 159 343 344 #define SRST_DDRPHY0 160 345 #define SRST_DDRPHY0_APB 161 346 #define SRST_DDRCTRL0 162 347 #define SRST_DDRCTRL0_APB 163 348 #define SRST_DDRPHY0_CTRL 164 349 #define SRST_DDRPHY1 165 350 #define SRST_DDRPHY1_APB 166 351 #define SRST_DDRCTRL1 167 352 #define SRST_DDRCTRL1_APB 168 353 #define SRST_DDRPHY1_CTRL 169 354 #define SRST_DDRMSCH0 170 355 #define SRST_DDRMSCH1 171 356 #define SRST_CRYPTO 174 357 #define SRST_C2C_HOST 175 358 359 #define SRST_LCDC1_AXI 176 360 #define SRST_LCDC1_AHB 177 361 #define SRST_LCDC1_DCLK 178 362 #define SRST_UART0 179 363 #define SRST_UART1 180 364 #define SRST_UART2 181 365 #define SRST_UART3 182 366 #define SRST_UART4 183 367 #define SRST_SIMC 186 368 #define SRST_PS2C 187 369 #define SRST_TSP 188 370 #define SRST_TSP_CLKIN0 189 371 #define SRST_TSP_CLKIN1 190 372 #define SRST_TSP_27M 191 373