1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 9 10 /* core clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_GPLL 4 15 #define ARMCLK 5 16 17 /* sclk gates (special clocks) */ 18 #define SCLK_SPI0 65 19 #define SCLK_NANDC 67 20 #define SCLK_SDMMC 68 21 #define SCLK_SDIO 69 22 #define SCLK_EMMC 71 23 #define SCLK_TSADC 72 24 #define SCLK_UART0 77 25 #define SCLK_UART1 78 26 #define SCLK_UART2 79 27 #define SCLK_I2S0 80 28 #define SCLK_I2S1 81 29 #define SCLK_I2S2 82 30 #define SCLK_SPDIF 83 31 #define SCLK_TIMER0 85 32 #define SCLK_TIMER1 86 33 #define SCLK_TIMER2 87 34 #define SCLK_TIMER3 88 35 #define SCLK_TIMER4 89 36 #define SCLK_TIMER5 90 37 #define SCLK_I2S_OUT 113 38 #define SCLK_SDMMC_DRV 114 39 #define SCLK_SDIO_DRV 115 40 #define SCLK_EMMC_DRV 117 41 #define SCLK_SDMMC_SAMPLE 118 42 #define SCLK_SDIO_SAMPLE 119 43 #define SCLK_EMMC_SAMPLE 121 44 #define SCLK_VOP 122 45 #define SCLK_HDMI_HDCP 123 46 #define SCLK_MAC_SRC 124 47 #define SCLK_MAC_EXTCLK 125 48 #define SCLK_MAC 126 49 #define SCLK_MAC_REFOUT 127 50 #define SCLK_MAC_REF 128 51 #define SCLK_MAC_RX 129 52 #define SCLK_MAC_TX 130 53 #define SCLK_MAC_PHY 131 54 #define SCLK_MAC_OUT 132 55 56 /* dclk gates */ 57 #define DCLK_VOP 190 58 #define DCLK_HDMI_PHY 191 59 60 /* aclk gates */ 61 #define ACLK_DMAC 194 62 #define ACLK_PERI 210 63 #define ACLK_VOP 211 64 #define ACLK_GMAC 212 65 66 /* pclk gates */ 67 #define PCLK_GPIO0 320 68 #define PCLK_GPIO1 321 69 #define PCLK_GPIO2 322 70 #define PCLK_GPIO3 323 71 #define PCLK_GRF 329 72 #define PCLK_I2C0 332 73 #define PCLK_I2C1 333 74 #define PCLK_I2C2 334 75 #define PCLK_I2C3 335 76 #define PCLK_SPI0 338 77 #define PCLK_UART0 341 78 #define PCLK_UART1 342 79 #define PCLK_UART2 343 80 #define PCLK_TSADC 344 81 #define PCLK_PWM 350 82 #define PCLK_TIMER 353 83 #define PCLK_PERI 363 84 #define PCLK_HDMI_CTRL 364 85 #define PCLK_HDMI_PHY 365 86 #define PCLK_GMAC 367 87 88 /* hclk gates */ 89 #define HCLK_I2S0_8CH 442 90 #define HCLK_I2S1_8CH 443 91 #define HCLK_I2S2_2CH 444 92 #define HCLK_SPDIF_8CH 445 93 #define HCLK_VOP 452 94 #define HCLK_NANDC 453 95 #define HCLK_SDMMC 456 96 #define HCLK_SDIO 457 97 #define HCLK_EMMC 459 98 #define HCLK_PERI 478 99 100 #define CLK_NR_CLKS (HCLK_PERI + 1) 101 102 #define PCLK_EFUSE_256 327 103 104 /* soft-reset indices */ 105 #define SRST_CORE0_PO 0 106 #define SRST_CORE1_PO 1 107 #define SRST_CORE2_PO 2 108 #define SRST_CORE3_PO 3 109 #define SRST_CORE0 4 110 #define SRST_CORE1 5 111 #define SRST_CORE2 6 112 #define SRST_CORE3 7 113 #define SRST_CORE0_DBG 8 114 #define SRST_CORE1_DBG 9 115 #define SRST_CORE2_DBG 10 116 #define SRST_CORE3_DBG 11 117 #define SRST_TOPDBG 12 118 #define SRST_ACLK_CORE 13 119 #define SRST_NOC 14 120 #define SRST_L2C 15 121 122 #define SRST_CPUSYS_H 18 123 #define SRST_BUSSYS_H 19 124 #define SRST_SPDIF 20 125 #define SRST_INTMEM 21 126 #define SRST_ROM 22 127 #define SRST_OTG_ADP 23 128 #define SRST_I2S0 24 129 #define SRST_I2S1 25 130 #define SRST_I2S2 26 131 #define SRST_ACODEC_P 27 132 #define SRST_DFIMON 28 133 #define SRST_MSCH 29 134 #define SRST_EFUSE1024 30 135 #define SRST_EFUSE256 31 136 137 #define SRST_GPIO0 32 138 #define SRST_GPIO1 33 139 #define SRST_GPIO2 34 140 #define SRST_GPIO3 35 141 #define SRST_PERIPH_NOC_A 36 142 #define SRST_PERIPH_NOC_BUS_H 37 143 #define SRST_PERIPH_NOC_P 38 144 #define SRST_UART0 39 145 #define SRST_UART1 40 146 #define SRST_UART2 41 147 #define SRST_PHYNOC 42 148 #define SRST_I2C0 43 149 #define SRST_I2C1 44 150 #define SRST_I2C2 45 151 #define SRST_I2C3 46 152 153 #define SRST_PWM 48 154 #define SRST_A53_GIC 49 155 #define SRST_DAP 51 156 #define SRST_DAP_NOC 52 157 #define SRST_CRYPTO 53 158 #define SRST_SGRF 54 159 #define SRST_GRF 55 160 #define SRST_GMAC 56 161 #define SRST_PERIPH_NOC_H 58 162 #define SRST_MACPHY 63 163 164 #define SRST_DMA 64 165 #define SRST_NANDC 68 166 #define SRST_USBOTG 69 167 #define SRST_OTGC 70 168 #define SRST_USBHOST0 71 169 #define SRST_HOST_CTRL0 72 170 #define SRST_USBHOST1 73 171 #define SRST_HOST_CTRL1 74 172 #define SRST_USBHOST2 75 173 #define SRST_HOST_CTRL2 76 174 #define SRST_USBPOR0 77 175 #define SRST_USBPOR1 78 176 #define SRST_DDRMSCH 79 177 178 #define SRST_SMART_CARD 80 179 #define SRST_SDMMC 81 180 #define SRST_SDIO 82 181 #define SRST_EMMC 83 182 #define SRST_SPI 84 183 #define SRST_TSP_H 85 184 #define SRST_TSP 86 185 #define SRST_TSADC 87 186 #define SRST_DDRPHY 88 187 #define SRST_DDRPHY_P 89 188 #define SRST_DDRCTRL 90 189 #define SRST_DDRCTRL_P 91 190 #define SRST_HOST0_ECHI 92 191 #define SRST_HOST1_ECHI 93 192 #define SRST_HOST2_ECHI 94 193 #define SRST_VOP_NOC_A 95 194 195 #define SRST_HDMI_P 96 196 #define SRST_VIO_ARBI_H 97 197 #define SRST_IEP_NOC_A 98 198 #define SRST_VIO_NOC_H 99 199 #define SRST_VOP_A 100 200 #define SRST_VOP_H 101 201 #define SRST_VOP_D 102 202 #define SRST_UTMI0 103 203 #define SRST_UTMI1 104 204 #define SRST_UTMI2 105 205 #define SRST_UTMI3 106 206 #define SRST_RGA 107 207 #define SRST_RGA_NOC_A 108 208 #define SRST_RGA_A 109 209 #define SRST_RGA_H 110 210 #define SRST_HDCP_A 111 211 212 #define SRST_VPU_A 112 213 #define SRST_VPU_H 113 214 #define SRST_VPU_NOC_A 116 215 #define SRST_VPU_NOC_H 117 216 #define SRST_RKVDEC_A 118 217 #define SRST_RKVDEC_NOC_A 119 218 #define SRST_RKVDEC_H 120 219 #define SRST_RKVDEC_NOC_H 121 220 #define SRST_RKVDEC_CORE 122 221 #define SRST_RKVDEC_CABAC 123 222 #define SRST_IEP_A 124 223 #define SRST_IEP_H 125 224 #define SRST_GPU_A 126 225 #define SRST_GPU_NOC_A 127 226 227 #define SRST_CORE_DBG 128 228 #define SRST_DBG_P 129 229 #define SRST_TIMER0 130 230 #define SRST_TIMER1 131 231 #define SRST_TIMER2 132 232 #define SRST_TIMER3 133 233 #define SRST_TIMER4 134 234 #define SRST_TIMER5 135 235 #define SRST_VIO_H2P 136 236 #define SRST_HDMIPHY 139 237 #define SRST_VDAC 140 238 #define SRST_TIMER_6CH_P 141 239 240 #endif 241