114e4b149Smaxims@google.com /* 214e4b149Smaxims@google.com * Copyright 2016 Google Inc. 314e4b149Smaxims@google.com * 414e4b149Smaxims@google.com * SPDX-License-Identifier: GPL-2.0+ 514e4b149Smaxims@google.com */ 614e4b149Smaxims@google.com 714e4b149Smaxims@google.com /* Core Clocks */ 814e4b149Smaxims@google.com #define PLL_HPLL 1 914e4b149Smaxims@google.com #define PLL_DPLL 2 1014e4b149Smaxims@google.com #define PLL_D2PLL 3 1114e4b149Smaxims@google.com #define PLL_MPLL 4 1214e4b149Smaxims@google.com #define ARMCLK 5 1314e4b149Smaxims@google.com 1414e4b149Smaxims@google.com 1514e4b149Smaxims@google.com /* Bus Clocks, derived from core clocks */ 1614e4b149Smaxims@google.com #define BCLK_PCLK 101 1714e4b149Smaxims@google.com #define BCLK_LHCLK 102 1814e4b149Smaxims@google.com #define BCLK_MACCLK 103 1914e4b149Smaxims@google.com #define BCLK_SDCLK 104 2014e4b149Smaxims@google.com #define BCLK_ARMCLK 105 2114e4b149Smaxims@google.com 2214e4b149Smaxims@google.com #define MCLK_DDR 201 2314e4b149Smaxims@google.com 2414e4b149Smaxims@google.com /* Special clocks */ 2514e4b149Smaxims@google.com #define PCLK_UART1 501 2614e4b149Smaxims@google.com #define PCLK_UART2 502 2714e4b149Smaxims@google.com #define PCLK_UART3 503 2814e4b149Smaxims@google.com #define PCLK_UART4 504 2914e4b149Smaxims@google.com #define PCLK_UART5 505 30*3b95902dSmaxims@google.com #define PCLK_MAC1 506 31*3b95902dSmaxims@google.com #define PCLK_MAC2 507 32