1 /* 2 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DRM_MODES_H 8 #define _DRM_MODES_H 9 10 /* Video mode flags */ 11 /* bit compatible with the xorg definitions. */ 12 #define DRM_MODE_FLAG_PHSYNC (1 << 0) 13 #define DRM_MODE_FLAG_NHSYNC (1 << 1) 14 #define DRM_MODE_FLAG_PVSYNC (1 << 2) 15 #define DRM_MODE_FLAG_NVSYNC (1 << 3) 16 #define DRM_MODE_FLAG_INTERLACE (1 << 4) 17 #define DRM_MODE_FLAG_DBLSCAN (1 << 5) 18 #define DRM_MODE_FLAG_CSYNC (1 << 6) 19 #define DRM_MODE_FLAG_PCSYNC (1 << 7) 20 #define DRM_MODE_FLAG_NCSYNC (1 << 8) 21 #define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ 22 #define DRM_MODE_FLAG_BCAST (1 << 10) 23 #define DRM_MODE_FLAG_PIXMUX (1 << 11) 24 #define DRM_MODE_FLAG_DBLCLK (1 << 12) 25 #define DRM_MODE_FLAG_CLKDIV2 (1 << 13) 26 27 #define DRM_MODE_CONNECTOR_Unknown 0 28 #define DRM_MODE_CONNECTOR_VGA 1 29 #define DRM_MODE_CONNECTOR_DVII 2 30 #define DRM_MODE_CONNECTOR_DVID 3 31 #define DRM_MODE_CONNECTOR_DVIA 4 32 #define DRM_MODE_CONNECTOR_Composite 5 33 #define DRM_MODE_CONNECTOR_SVIDEO 6 34 #define DRM_MODE_CONNECTOR_LVDS 7 35 #define DRM_MODE_CONNECTOR_Component 8 36 #define DRM_MODE_CONNECTOR_9PinDIN 9 37 #define DRM_MODE_CONNECTOR_DisplayPort 10 38 #define DRM_MODE_CONNECTOR_HDMIA 11 39 #define DRM_MODE_CONNECTOR_HDMIB 12 40 #define DRM_MODE_CONNECTOR_TV 13 41 #define DRM_MODE_CONNECTOR_eDP 14 42 #define DRM_MODE_CONNECTOR_VIRTUAL 15 43 #define DRM_MODE_CONNECTOR_DSI 16 44 45 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 46 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 47 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 48 #define DRM_EDID_PT_STEREO (1 << 5) 49 #define DRM_EDID_PT_INTERLACED (1 << 7) 50 51 struct drm_display_mode { 52 /* Proposed mode values */ 53 int clock; /* in kHz */ 54 int hdisplay; 55 int hsync_start; 56 int hsync_end; 57 int htotal; 58 int vdisplay; 59 int vsync_start; 60 int vsync_end; 61 int vtotal; 62 int vrefresh; 63 int vscan; 64 unsigned int flags; 65 }; 66 67 #endif 68