1 /* 2 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DRM_MODES_H 8 #define _DRM_MODES_H 9 10 #define DRM_DISPLAY_INFO_LEN 32 11 #define DRM_CONNECTOR_NAME_LEN 32 12 #define DRM_DISPLAY_MODE_LEN 32 13 #define DRM_PROP_NAME_LEN 32 14 15 #define DRM_MODE_TYPE_BUILTIN (1<<0) 16 #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 17 #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 18 #define DRM_MODE_TYPE_PREFERRED (1<<3) 19 #define DRM_MODE_TYPE_DEFAULT (1<<4) 20 #define DRM_MODE_TYPE_USERDEF (1<<5) 21 #define DRM_MODE_TYPE_DRIVER (1<<6) 22 23 /* Video mode flags */ 24 /* bit compatible with the xorg definitions. */ 25 #define DRM_MODE_FLAG_PHSYNC (1 << 0) 26 #define DRM_MODE_FLAG_NHSYNC (1 << 1) 27 #define DRM_MODE_FLAG_PVSYNC (1 << 2) 28 #define DRM_MODE_FLAG_NVSYNC (1 << 3) 29 #define DRM_MODE_FLAG_INTERLACE (1 << 4) 30 #define DRM_MODE_FLAG_DBLSCAN (1 << 5) 31 #define DRM_MODE_FLAG_CSYNC (1 << 6) 32 #define DRM_MODE_FLAG_PCSYNC (1 << 7) 33 #define DRM_MODE_FLAG_NCSYNC (1 << 8) 34 #define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ 35 #define DRM_MODE_FLAG_BCAST (1 << 10) 36 #define DRM_MODE_FLAG_PIXMUX (1 << 11) 37 #define DRM_MODE_FLAG_DBLCLK (1 << 12) 38 #define DRM_MODE_FLAG_CLKDIV2 (1 << 13) 39 #define DRM_MODE_FLAG_PPIXDATA BIT(31) 40 41 /* Panel Mirror control */ 42 #define DRM_MODE_FLAG_XMIRROR (1<<28) 43 #define DRM_MODE_FLAG_YMIRROR (1<<29) 44 #define DRM_MODE_FLAG_XYMIRROR (DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR) 45 46 #define DRM_MODE_CONNECTOR_Unknown 0 47 #define DRM_MODE_CONNECTOR_VGA 1 48 #define DRM_MODE_CONNECTOR_DVII 2 49 #define DRM_MODE_CONNECTOR_DVID 3 50 #define DRM_MODE_CONNECTOR_DVIA 4 51 #define DRM_MODE_CONNECTOR_Composite 5 52 #define DRM_MODE_CONNECTOR_SVIDEO 6 53 #define DRM_MODE_CONNECTOR_LVDS 7 54 #define DRM_MODE_CONNECTOR_Component 8 55 #define DRM_MODE_CONNECTOR_9PinDIN 9 56 #define DRM_MODE_CONNECTOR_DisplayPort 10 57 #define DRM_MODE_CONNECTOR_HDMIA 11 58 #define DRM_MODE_CONNECTOR_HDMIB 12 59 #define DRM_MODE_CONNECTOR_TV 13 60 #define DRM_MODE_CONNECTOR_eDP 14 61 #define DRM_MODE_CONNECTOR_VIRTUAL 15 62 #define DRM_MODE_CONNECTOR_DSI 16 63 64 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 65 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 66 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 67 #define DRM_EDID_PT_STEREO (1 << 5) 68 #define DRM_EDID_PT_INTERLACED (1 << 7) 69 70 /* see also http://vektor.theorem.ca/graphics/ycbcr/ */ 71 enum v4l2_colorspace { 72 /* 73 * Default colorspace, i.e. let the driver figure it out. 74 * Can only be used with video capture. 75 */ 76 V4L2_COLORSPACE_DEFAULT = 0, 77 78 /* SMPTE 170M: used for broadcast NTSC/PAL SDTV */ 79 V4L2_COLORSPACE_SMPTE170M = 1, 80 81 /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */ 82 V4L2_COLORSPACE_SMPTE240M = 2, 83 84 /* Rec.709: used for HDTV */ 85 V4L2_COLORSPACE_REC709 = 3, 86 87 /* 88 * Deprecated, do not use. No driver will ever return this. This was 89 * based on a misunderstanding of the bt878 datasheet. 90 */ 91 V4L2_COLORSPACE_BT878 = 4, 92 93 /* 94 * NTSC 1953 colorspace. This only makes sense when dealing with 95 * really, really old NTSC recordings. Superseded by SMPTE 170M. 96 */ 97 V4L2_COLORSPACE_470_SYSTEM_M = 5, 98 99 /* 100 * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when 101 * dealing with really old PAL/SECAM recordings. Superseded by 102 * SMPTE 170M. 103 */ 104 V4L2_COLORSPACE_470_SYSTEM_BG = 6, 105 106 /* 107 * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601 108 * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG. 109 */ 110 V4L2_COLORSPACE_JPEG = 7, 111 112 /* For RGB colorspaces such as produces by most webcams. */ 113 V4L2_COLORSPACE_SRGB = 8, 114 115 /* AdobeRGB colorspace */ 116 V4L2_COLORSPACE_ADOBERGB = 9, 117 118 /* BT.2020 colorspace, used for UHDTV. */ 119 V4L2_COLORSPACE_BT2020 = 10, 120 121 /* Raw colorspace: for RAW unprocessed images */ 122 V4L2_COLORSPACE_RAW = 11, 123 124 /* DCI-P3 colorspace, used by cinema projectors */ 125 V4L2_COLORSPACE_DCI_P3 = 12, 126 }; 127 128 #define CRTC_INTERLACE_HALVE_V (1 << 0) /* halve V values for interlacing */ 129 #define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */ 130 #define CRTC_NO_DBLSCAN (1 << 2) /* don't adjust doublescan */ 131 #define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */ 132 #define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \ 133 CRTC_NO_VSCAN) 134 135 #define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF 136 137 struct drm_display_mode { 138 /* Proposed mode values */ 139 int clock; /* in kHz */ 140 int hdisplay; 141 int hsync_start; 142 int hsync_end; 143 int htotal; 144 int vdisplay; 145 int vsync_start; 146 int vsync_end; 147 int vtotal; 148 int vrefresh; 149 int vscan; 150 unsigned int flags; 151 int picture_aspect_ratio; 152 int hskew; 153 unsigned int type; 154 /* Actual mode we give to hw */ 155 int crtc_clock; /* in KHz */ 156 int crtc_hdisplay; 157 int crtc_hblank_start; 158 int crtc_hblank_end; 159 int crtc_hsync_start; 160 int crtc_hsync_end; 161 int crtc_htotal; 162 int crtc_hskew; 163 int crtc_vdisplay; 164 int crtc_vblank_start; 165 int crtc_vblank_end; 166 int crtc_vsync_start; 167 int crtc_vsync_end; 168 int crtc_vtotal; 169 bool invalid; 170 }; 171 172 #endif 173