1 /* 2 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DRM_MODES_H 8 #define _DRM_MODES_H 9 10 #define DRM_DISPLAY_INFO_LEN 32 11 #define DRM_CONNECTOR_NAME_LEN 32 12 #define DRM_DISPLAY_MODE_LEN 32 13 #define DRM_PROP_NAME_LEN 32 14 15 #define DRM_MODE_TYPE_BUILTIN (1<<0) 16 #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 17 #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 18 #define DRM_MODE_TYPE_PREFERRED (1<<3) 19 #define DRM_MODE_TYPE_DEFAULT (1<<4) 20 #define DRM_MODE_TYPE_USERDEF (1<<5) 21 #define DRM_MODE_TYPE_DRIVER (1<<6) 22 23 /* Video mode flags */ 24 /* bit compatible with the xorg definitions. */ 25 #define DRM_MODE_FLAG_PHSYNC (1 << 0) 26 #define DRM_MODE_FLAG_NHSYNC (1 << 1) 27 #define DRM_MODE_FLAG_PVSYNC (1 << 2) 28 #define DRM_MODE_FLAG_NVSYNC (1 << 3) 29 #define DRM_MODE_FLAG_INTERLACE (1 << 4) 30 #define DRM_MODE_FLAG_DBLSCAN (1 << 5) 31 #define DRM_MODE_FLAG_CSYNC (1 << 6) 32 #define DRM_MODE_FLAG_PCSYNC (1 << 7) 33 #define DRM_MODE_FLAG_NCSYNC (1 << 8) 34 #define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ 35 #define DRM_MODE_FLAG_BCAST (1 << 10) 36 #define DRM_MODE_FLAG_PIXMUX (1 << 11) 37 #define DRM_MODE_FLAG_DBLCLK (1 << 12) 38 #define DRM_MODE_FLAG_CLKDIV2 (1 << 13) 39 #define DRM_MODE_FLAG_PPIXDATA BIT(31) 40 41 #define DRM_MODE_CONNECTOR_Unknown 0 42 #define DRM_MODE_CONNECTOR_VGA 1 43 #define DRM_MODE_CONNECTOR_DVII 2 44 #define DRM_MODE_CONNECTOR_DVID 3 45 #define DRM_MODE_CONNECTOR_DVIA 4 46 #define DRM_MODE_CONNECTOR_Composite 5 47 #define DRM_MODE_CONNECTOR_SVIDEO 6 48 #define DRM_MODE_CONNECTOR_LVDS 7 49 #define DRM_MODE_CONNECTOR_Component 8 50 #define DRM_MODE_CONNECTOR_9PinDIN 9 51 #define DRM_MODE_CONNECTOR_DisplayPort 10 52 #define DRM_MODE_CONNECTOR_HDMIA 11 53 #define DRM_MODE_CONNECTOR_HDMIB 12 54 #define DRM_MODE_CONNECTOR_TV 13 55 #define DRM_MODE_CONNECTOR_eDP 14 56 #define DRM_MODE_CONNECTOR_VIRTUAL 15 57 #define DRM_MODE_CONNECTOR_DSI 16 58 59 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 60 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 61 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 62 #define DRM_EDID_PT_STEREO (1 << 5) 63 #define DRM_EDID_PT_INTERLACED (1 << 7) 64 65 /* see also http://vektor.theorem.ca/graphics/ycbcr/ */ 66 enum v4l2_colorspace { 67 /* 68 * Default colorspace, i.e. let the driver figure it out. 69 * Can only be used with video capture. 70 */ 71 V4L2_COLORSPACE_DEFAULT = 0, 72 73 /* SMPTE 170M: used for broadcast NTSC/PAL SDTV */ 74 V4L2_COLORSPACE_SMPTE170M = 1, 75 76 /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */ 77 V4L2_COLORSPACE_SMPTE240M = 2, 78 79 /* Rec.709: used for HDTV */ 80 V4L2_COLORSPACE_REC709 = 3, 81 82 /* 83 * Deprecated, do not use. No driver will ever return this. This was 84 * based on a misunderstanding of the bt878 datasheet. 85 */ 86 V4L2_COLORSPACE_BT878 = 4, 87 88 /* 89 * NTSC 1953 colorspace. This only makes sense when dealing with 90 * really, really old NTSC recordings. Superseded by SMPTE 170M. 91 */ 92 V4L2_COLORSPACE_470_SYSTEM_M = 5, 93 94 /* 95 * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when 96 * dealing with really old PAL/SECAM recordings. Superseded by 97 * SMPTE 170M. 98 */ 99 V4L2_COLORSPACE_470_SYSTEM_BG = 6, 100 101 /* 102 * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601 103 * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG. 104 */ 105 V4L2_COLORSPACE_JPEG = 7, 106 107 /* For RGB colorspaces such as produces by most webcams. */ 108 V4L2_COLORSPACE_SRGB = 8, 109 110 /* AdobeRGB colorspace */ 111 V4L2_COLORSPACE_ADOBERGB = 9, 112 113 /* BT.2020 colorspace, used for UHDTV. */ 114 V4L2_COLORSPACE_BT2020 = 10, 115 116 /* Raw colorspace: for RAW unprocessed images */ 117 V4L2_COLORSPACE_RAW = 11, 118 119 /* DCI-P3 colorspace, used by cinema projectors */ 120 V4L2_COLORSPACE_DCI_P3 = 12, 121 }; 122 123 #define CRTC_INTERLACE_HALVE_V (1 << 0) /* halve V values for interlacing */ 124 #define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */ 125 #define CRTC_NO_DBLSCAN (1 << 2) /* don't adjust doublescan */ 126 #define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */ 127 #define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \ 128 CRTC_NO_VSCAN) 129 130 #define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF 131 132 struct drm_display_mode { 133 /* Proposed mode values */ 134 int clock; /* in kHz */ 135 int hdisplay; 136 int hsync_start; 137 int hsync_end; 138 int htotal; 139 int vdisplay; 140 int vsync_start; 141 int vsync_end; 142 int vtotal; 143 int vrefresh; 144 int vscan; 145 unsigned int flags; 146 int picture_aspect_ratio; 147 int hskew; 148 unsigned int type; 149 /* Actual mode we give to hw */ 150 int crtc_clock; /* in KHz */ 151 int crtc_hdisplay; 152 int crtc_hblank_start; 153 int crtc_hblank_end; 154 int crtc_hsync_start; 155 int crtc_hsync_end; 156 int crtc_htotal; 157 int crtc_hskew; 158 int crtc_vdisplay; 159 int crtc_vblank_start; 160 int crtc_vblank_end; 161 int crtc_vsync_start; 162 int crtc_vsync_end; 163 int crtc_vtotal; 164 bool invalid; 165 }; 166 167 #endif 168