1 /* 2 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DRM_MODES_H 8 #define _DRM_MODES_H 9 10 #define DRM_MODE_TYPE_BUILTIN BIT(0) 11 #define DRM_MODE_TYPE_CLOCK_C (BIT(1) | DRM_MODE_TYPE_BUILTIN) 12 #define DRM_MODE_TYPE_CRTC_C (BIT(2) | DRM_MODE_TYPE_BUILTIN) 13 #define DRM_MODE_TYPE_PREFERRED BIT(3) 14 #define DRM_MODE_TYPE_DEFAULT BIT(4) 15 #define DRM_MODE_TYPE_USERDEF BIT(5) 16 #define DRM_MODE_TYPE_DRIVER BIT(6) 17 18 /* Video mode flags */ 19 /* bit compatible with the xorg definitions. */ 20 #define DRM_MODE_FLAG_PHSYNC (1 << 0) 21 #define DRM_MODE_FLAG_NHSYNC (1 << 1) 22 #define DRM_MODE_FLAG_PVSYNC (1 << 2) 23 #define DRM_MODE_FLAG_NVSYNC (1 << 3) 24 #define DRM_MODE_FLAG_INTERLACE (1 << 4) 25 #define DRM_MODE_FLAG_DBLSCAN (1 << 5) 26 #define DRM_MODE_FLAG_CSYNC (1 << 6) 27 #define DRM_MODE_FLAG_PCSYNC (1 << 7) 28 #define DRM_MODE_FLAG_NCSYNC (1 << 8) 29 #define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ 30 #define DRM_MODE_FLAG_BCAST (1 << 10) 31 #define DRM_MODE_FLAG_PIXMUX (1 << 11) 32 #define DRM_MODE_FLAG_DBLCLK (1 << 12) 33 #define DRM_MODE_FLAG_CLKDIV2 (1 << 13) 34 35 #define DRM_MODE_CONNECTOR_Unknown 0 36 #define DRM_MODE_CONNECTOR_VGA 1 37 #define DRM_MODE_CONNECTOR_DVII 2 38 #define DRM_MODE_CONNECTOR_DVID 3 39 #define DRM_MODE_CONNECTOR_DVIA 4 40 #define DRM_MODE_CONNECTOR_Composite 5 41 #define DRM_MODE_CONNECTOR_SVIDEO 6 42 #define DRM_MODE_CONNECTOR_LVDS 7 43 #define DRM_MODE_CONNECTOR_Component 8 44 #define DRM_MODE_CONNECTOR_9PinDIN 9 45 #define DRM_MODE_CONNECTOR_DisplayPort 10 46 #define DRM_MODE_CONNECTOR_HDMIA 11 47 #define DRM_MODE_CONNECTOR_HDMIB 12 48 #define DRM_MODE_CONNECTOR_TV 13 49 #define DRM_MODE_CONNECTOR_eDP 14 50 #define DRM_MODE_CONNECTOR_VIRTUAL 15 51 #define DRM_MODE_CONNECTOR_DSI 16 52 53 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 54 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 55 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 56 #define DRM_EDID_PT_STEREO (1 << 5) 57 #define DRM_EDID_PT_INTERLACED (1 << 7) 58 59 struct drm_display_mode { 60 /* Proposed mode values */ 61 int clock; /* in kHz */ 62 int hdisplay; 63 int hsync_start; 64 int hsync_end; 65 int htotal; 66 int vdisplay; 67 int vsync_start; 68 int vsync_end; 69 int vtotal; 70 int vrefresh; 71 int vscan; 72 unsigned int flags; 73 int picture_aspect_ratio; 74 }; 75 76 #endif 77