1b9e63a96SMark Yao /* 2b9e63a96SMark Yao * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 3b9e63a96SMark Yao * 4b9e63a96SMark Yao * SPDX-License-Identifier: GPL-2.0+ 5b9e63a96SMark Yao */ 6b9e63a96SMark Yao 7b9e63a96SMark Yao #ifndef _DRM_MODES_H 8b9e63a96SMark Yao #define _DRM_MODES_H 9b9e63a96SMark Yao 10ccd843b9SSandy Huang #define DRM_DISPLAY_INFO_LEN 32 11ccd843b9SSandy Huang #define DRM_CONNECTOR_NAME_LEN 32 12ccd843b9SSandy Huang #define DRM_DISPLAY_MODE_LEN 32 13ccd843b9SSandy Huang #define DRM_PROP_NAME_LEN 32 14ccd843b9SSandy Huang 15ccd843b9SSandy Huang #define DRM_MODE_TYPE_BUILTIN (1<<0) 16ccd843b9SSandy Huang #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 17ccd843b9SSandy Huang #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 18ccd843b9SSandy Huang #define DRM_MODE_TYPE_PREFERRED (1<<3) 19ccd843b9SSandy Huang #define DRM_MODE_TYPE_DEFAULT (1<<4) 20ccd843b9SSandy Huang #define DRM_MODE_TYPE_USERDEF (1<<5) 21ccd843b9SSandy Huang #define DRM_MODE_TYPE_DRIVER (1<<6) 2221016d27SAlgea Cao 23b9e63a96SMark Yao /* Video mode flags */ 24b9e63a96SMark Yao /* bit compatible with the xorg definitions. */ 25b9e63a96SMark Yao #define DRM_MODE_FLAG_PHSYNC (1 << 0) 26b9e63a96SMark Yao #define DRM_MODE_FLAG_NHSYNC (1 << 1) 27b9e63a96SMark Yao #define DRM_MODE_FLAG_PVSYNC (1 << 2) 28b9e63a96SMark Yao #define DRM_MODE_FLAG_NVSYNC (1 << 3) 29b9e63a96SMark Yao #define DRM_MODE_FLAG_INTERLACE (1 << 4) 30b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLSCAN (1 << 5) 31b9e63a96SMark Yao #define DRM_MODE_FLAG_CSYNC (1 << 6) 32b9e63a96SMark Yao #define DRM_MODE_FLAG_PCSYNC (1 << 7) 33b9e63a96SMark Yao #define DRM_MODE_FLAG_NCSYNC (1 << 8) 34b9e63a96SMark Yao #define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ 35b9e63a96SMark Yao #define DRM_MODE_FLAG_BCAST (1 << 10) 36b9e63a96SMark Yao #define DRM_MODE_FLAG_PIXMUX (1 << 11) 37b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLCLK (1 << 12) 38b9e63a96SMark Yao #define DRM_MODE_FLAG_CLKDIV2 (1 << 13) 398e2bab3fSAlgea Cao #define DRM_MODE_FLAG_PPIXDATA BIT(31) 40b9e63a96SMark Yao 41ffa55e18SShixiang Zheng /* Panel Mirror control */ 42ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_XMIRROR (1<<28) 43ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_YMIRROR (1<<29) 44ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_XYMIRROR (DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR) 4594d85f7bSSandy Huang 4694d85f7bSSandy Huang /* Picture aspect ratio options */ 4794d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_NONE 0 4894d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_4_3 1 4994d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_16_9 2 5094d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_64_27 3 5194d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_256_135 4 5294d85f7bSSandy Huang 5394d85f7bSSandy Huang /* Aspect ratio flag bitmask (4 bits 22:19) */ 5494d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19) 5594d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_NONE \ 5694d85f7bSSandy Huang (DRM_MODE_PICTURE_ASPECT_NONE << 19) 5794d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_4_3 \ 5894d85f7bSSandy Huang (DRM_MODE_PICTURE_ASPECT_4_3 << 19) 5994d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_16_9 \ 6094d85f7bSSandy Huang (DRM_MODE_PICTURE_ASPECT_16_9 << 19) 6194d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_64_27 \ 6294d85f7bSSandy Huang (DRM_MODE_PICTURE_ASPECT_64_27 << 19) 6394d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_256_135 \ 6494d85f7bSSandy Huang (DRM_MODE_PICTURE_ASPECT_256_135 << 19) 65ffa55e18SShixiang Zheng 66b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Unknown 0 67b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VGA 1 68b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVII 2 69b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVID 3 70b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVIA 4 71b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Composite 5 72b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_SVIDEO 6 73b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_LVDS 7 74b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Component 8 75b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_9PinDIN 9 76b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DisplayPort 10 77b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIA 11 78b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIB 12 79b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_TV 13 80b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_eDP 14 81b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VIRTUAL 15 82b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DSI 16 83*ecc31b6eSAndy Yan #define DRM_MODE_CONNECTOR_DPI 17 84b9e63a96SMark Yao 85b9e63a96SMark Yao #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 86b9e63a96SMark Yao #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 87b9e63a96SMark Yao #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 88b9e63a96SMark Yao #define DRM_EDID_PT_STEREO (1 << 5) 89b9e63a96SMark Yao #define DRM_EDID_PT_INTERLACED (1 << 7) 90b9e63a96SMark Yao 9179feefb1SSandy Huang /* see also http://vektor.theorem.ca/graphics/ycbcr/ */ 9279feefb1SSandy Huang enum v4l2_colorspace { 9379feefb1SSandy Huang /* 9479feefb1SSandy Huang * Default colorspace, i.e. let the driver figure it out. 9579feefb1SSandy Huang * Can only be used with video capture. 9679feefb1SSandy Huang */ 9779feefb1SSandy Huang V4L2_COLORSPACE_DEFAULT = 0, 9879feefb1SSandy Huang 9979feefb1SSandy Huang /* SMPTE 170M: used for broadcast NTSC/PAL SDTV */ 10079feefb1SSandy Huang V4L2_COLORSPACE_SMPTE170M = 1, 10179feefb1SSandy Huang 10279feefb1SSandy Huang /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */ 10379feefb1SSandy Huang V4L2_COLORSPACE_SMPTE240M = 2, 10479feefb1SSandy Huang 10579feefb1SSandy Huang /* Rec.709: used for HDTV */ 10679feefb1SSandy Huang V4L2_COLORSPACE_REC709 = 3, 10779feefb1SSandy Huang 10879feefb1SSandy Huang /* 10979feefb1SSandy Huang * Deprecated, do not use. No driver will ever return this. This was 11079feefb1SSandy Huang * based on a misunderstanding of the bt878 datasheet. 11179feefb1SSandy Huang */ 11279feefb1SSandy Huang V4L2_COLORSPACE_BT878 = 4, 11379feefb1SSandy Huang 11479feefb1SSandy Huang /* 11579feefb1SSandy Huang * NTSC 1953 colorspace. This only makes sense when dealing with 11679feefb1SSandy Huang * really, really old NTSC recordings. Superseded by SMPTE 170M. 11779feefb1SSandy Huang */ 11879feefb1SSandy Huang V4L2_COLORSPACE_470_SYSTEM_M = 5, 11979feefb1SSandy Huang 12079feefb1SSandy Huang /* 12179feefb1SSandy Huang * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when 12279feefb1SSandy Huang * dealing with really old PAL/SECAM recordings. Superseded by 12379feefb1SSandy Huang * SMPTE 170M. 12479feefb1SSandy Huang */ 12579feefb1SSandy Huang V4L2_COLORSPACE_470_SYSTEM_BG = 6, 12679feefb1SSandy Huang 12779feefb1SSandy Huang /* 12879feefb1SSandy Huang * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601 12979feefb1SSandy Huang * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG. 13079feefb1SSandy Huang */ 13179feefb1SSandy Huang V4L2_COLORSPACE_JPEG = 7, 13279feefb1SSandy Huang 13379feefb1SSandy Huang /* For RGB colorspaces such as produces by most webcams. */ 13479feefb1SSandy Huang V4L2_COLORSPACE_SRGB = 8, 13579feefb1SSandy Huang 13679feefb1SSandy Huang /* AdobeRGB colorspace */ 13779feefb1SSandy Huang V4L2_COLORSPACE_ADOBERGB = 9, 13879feefb1SSandy Huang 13979feefb1SSandy Huang /* BT.2020 colorspace, used for UHDTV. */ 14079feefb1SSandy Huang V4L2_COLORSPACE_BT2020 = 10, 14179feefb1SSandy Huang 14279feefb1SSandy Huang /* Raw colorspace: for RAW unprocessed images */ 14379feefb1SSandy Huang V4L2_COLORSPACE_RAW = 11, 14479feefb1SSandy Huang 14579feefb1SSandy Huang /* DCI-P3 colorspace, used by cinema projectors */ 14679feefb1SSandy Huang V4L2_COLORSPACE_DCI_P3 = 12, 14779feefb1SSandy Huang }; 14879feefb1SSandy Huang 149ccd843b9SSandy Huang #define CRTC_INTERLACE_HALVE_V (1 << 0) /* halve V values for interlacing */ 150ccd843b9SSandy Huang #define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */ 151ccd843b9SSandy Huang #define CRTC_NO_DBLSCAN (1 << 2) /* don't adjust doublescan */ 152ccd843b9SSandy Huang #define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */ 1538e2bab3fSAlgea Cao #define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \ 1548e2bab3fSAlgea Cao CRTC_NO_VSCAN) 155ccd843b9SSandy Huang 156ccd843b9SSandy Huang #define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF 157ccd843b9SSandy Huang 158b9e63a96SMark Yao struct drm_display_mode { 159b9e63a96SMark Yao /* Proposed mode values */ 160b9e63a96SMark Yao int clock; /* in kHz */ 161b9e63a96SMark Yao int hdisplay; 162b9e63a96SMark Yao int hsync_start; 163b9e63a96SMark Yao int hsync_end; 164b9e63a96SMark Yao int htotal; 165b9e63a96SMark Yao int vdisplay; 166b9e63a96SMark Yao int vsync_start; 167b9e63a96SMark Yao int vsync_end; 168b9e63a96SMark Yao int vtotal; 169b9e63a96SMark Yao int vrefresh; 170b9e63a96SMark Yao int vscan; 171b9e63a96SMark Yao unsigned int flags; 17221016d27SAlgea Cao int picture_aspect_ratio; 173ccd843b9SSandy Huang int hskew; 174ccd843b9SSandy Huang unsigned int type; 175ccd843b9SSandy Huang /* Actual mode we give to hw */ 176ccd843b9SSandy Huang int crtc_clock; /* in KHz */ 177ccd843b9SSandy Huang int crtc_hdisplay; 178ccd843b9SSandy Huang int crtc_hblank_start; 179ccd843b9SSandy Huang int crtc_hblank_end; 180ccd843b9SSandy Huang int crtc_hsync_start; 181ccd843b9SSandy Huang int crtc_hsync_end; 182ccd843b9SSandy Huang int crtc_htotal; 183ccd843b9SSandy Huang int crtc_hskew; 184ccd843b9SSandy Huang int crtc_vdisplay; 185ccd843b9SSandy Huang int crtc_vblank_start; 186ccd843b9SSandy Huang int crtc_vblank_end; 187ccd843b9SSandy Huang int crtc_vsync_start; 188ccd843b9SSandy Huang int crtc_vsync_end; 189ccd843b9SSandy Huang int crtc_vtotal; 1908e2bab3fSAlgea Cao bool invalid; 191b9e63a96SMark Yao }; 192b9e63a96SMark Yao 193b9e63a96SMark Yao #endif 194