1b9e63a96SMark Yao /* 2b9e63a96SMark Yao * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 3b9e63a96SMark Yao * 4b9e63a96SMark Yao * SPDX-License-Identifier: GPL-2.0+ 5b9e63a96SMark Yao */ 6b9e63a96SMark Yao 7b9e63a96SMark Yao #ifndef _DRM_MODES_H 8b9e63a96SMark Yao #define _DRM_MODES_H 9b9e63a96SMark Yao 10*ccd843b9SSandy Huang #define DRM_DISPLAY_INFO_LEN 32 11*ccd843b9SSandy Huang #define DRM_CONNECTOR_NAME_LEN 32 12*ccd843b9SSandy Huang #define DRM_DISPLAY_MODE_LEN 32 13*ccd843b9SSandy Huang #define DRM_PROP_NAME_LEN 32 14*ccd843b9SSandy Huang 15*ccd843b9SSandy Huang #define DRM_MODE_TYPE_BUILTIN (1<<0) 16*ccd843b9SSandy Huang #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 17*ccd843b9SSandy Huang #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 18*ccd843b9SSandy Huang #define DRM_MODE_TYPE_PREFERRED (1<<3) 19*ccd843b9SSandy Huang #define DRM_MODE_TYPE_DEFAULT (1<<4) 20*ccd843b9SSandy Huang #define DRM_MODE_TYPE_USERDEF (1<<5) 21*ccd843b9SSandy Huang #define DRM_MODE_TYPE_DRIVER (1<<6) 2221016d27SAlgea Cao 23b9e63a96SMark Yao /* Video mode flags */ 24b9e63a96SMark Yao /* bit compatible with the xorg definitions. */ 25b9e63a96SMark Yao #define DRM_MODE_FLAG_PHSYNC (1 << 0) 26b9e63a96SMark Yao #define DRM_MODE_FLAG_NHSYNC (1 << 1) 27b9e63a96SMark Yao #define DRM_MODE_FLAG_PVSYNC (1 << 2) 28b9e63a96SMark Yao #define DRM_MODE_FLAG_NVSYNC (1 << 3) 29b9e63a96SMark Yao #define DRM_MODE_FLAG_INTERLACE (1 << 4) 30b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLSCAN (1 << 5) 31b9e63a96SMark Yao #define DRM_MODE_FLAG_CSYNC (1 << 6) 32b9e63a96SMark Yao #define DRM_MODE_FLAG_PCSYNC (1 << 7) 33b9e63a96SMark Yao #define DRM_MODE_FLAG_NCSYNC (1 << 8) 34b9e63a96SMark Yao #define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ 35b9e63a96SMark Yao #define DRM_MODE_FLAG_BCAST (1 << 10) 36b9e63a96SMark Yao #define DRM_MODE_FLAG_PIXMUX (1 << 11) 37b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLCLK (1 << 12) 38b9e63a96SMark Yao #define DRM_MODE_FLAG_CLKDIV2 (1 << 13) 39b9e63a96SMark Yao 40b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Unknown 0 41b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VGA 1 42b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVII 2 43b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVID 3 44b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVIA 4 45b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Composite 5 46b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_SVIDEO 6 47b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_LVDS 7 48b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Component 8 49b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_9PinDIN 9 50b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DisplayPort 10 51b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIA 11 52b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIB 12 53b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_TV 13 54b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_eDP 14 55b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VIRTUAL 15 56b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DSI 16 57b9e63a96SMark Yao 58b9e63a96SMark Yao #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 59b9e63a96SMark Yao #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 60b9e63a96SMark Yao #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 61b9e63a96SMark Yao #define DRM_EDID_PT_STEREO (1 << 5) 62b9e63a96SMark Yao #define DRM_EDID_PT_INTERLACED (1 << 7) 63b9e63a96SMark Yao 6479feefb1SSandy Huang /* see also http://vektor.theorem.ca/graphics/ycbcr/ */ 6579feefb1SSandy Huang enum v4l2_colorspace { 6679feefb1SSandy Huang /* 6779feefb1SSandy Huang * Default colorspace, i.e. let the driver figure it out. 6879feefb1SSandy Huang * Can only be used with video capture. 6979feefb1SSandy Huang */ 7079feefb1SSandy Huang V4L2_COLORSPACE_DEFAULT = 0, 7179feefb1SSandy Huang 7279feefb1SSandy Huang /* SMPTE 170M: used for broadcast NTSC/PAL SDTV */ 7379feefb1SSandy Huang V4L2_COLORSPACE_SMPTE170M = 1, 7479feefb1SSandy Huang 7579feefb1SSandy Huang /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */ 7679feefb1SSandy Huang V4L2_COLORSPACE_SMPTE240M = 2, 7779feefb1SSandy Huang 7879feefb1SSandy Huang /* Rec.709: used for HDTV */ 7979feefb1SSandy Huang V4L2_COLORSPACE_REC709 = 3, 8079feefb1SSandy Huang 8179feefb1SSandy Huang /* 8279feefb1SSandy Huang * Deprecated, do not use. No driver will ever return this. This was 8379feefb1SSandy Huang * based on a misunderstanding of the bt878 datasheet. 8479feefb1SSandy Huang */ 8579feefb1SSandy Huang V4L2_COLORSPACE_BT878 = 4, 8679feefb1SSandy Huang 8779feefb1SSandy Huang /* 8879feefb1SSandy Huang * NTSC 1953 colorspace. This only makes sense when dealing with 8979feefb1SSandy Huang * really, really old NTSC recordings. Superseded by SMPTE 170M. 9079feefb1SSandy Huang */ 9179feefb1SSandy Huang V4L2_COLORSPACE_470_SYSTEM_M = 5, 9279feefb1SSandy Huang 9379feefb1SSandy Huang /* 9479feefb1SSandy Huang * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when 9579feefb1SSandy Huang * dealing with really old PAL/SECAM recordings. Superseded by 9679feefb1SSandy Huang * SMPTE 170M. 9779feefb1SSandy Huang */ 9879feefb1SSandy Huang V4L2_COLORSPACE_470_SYSTEM_BG = 6, 9979feefb1SSandy Huang 10079feefb1SSandy Huang /* 10179feefb1SSandy Huang * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601 10279feefb1SSandy Huang * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG. 10379feefb1SSandy Huang */ 10479feefb1SSandy Huang V4L2_COLORSPACE_JPEG = 7, 10579feefb1SSandy Huang 10679feefb1SSandy Huang /* For RGB colorspaces such as produces by most webcams. */ 10779feefb1SSandy Huang V4L2_COLORSPACE_SRGB = 8, 10879feefb1SSandy Huang 10979feefb1SSandy Huang /* AdobeRGB colorspace */ 11079feefb1SSandy Huang V4L2_COLORSPACE_ADOBERGB = 9, 11179feefb1SSandy Huang 11279feefb1SSandy Huang /* BT.2020 colorspace, used for UHDTV. */ 11379feefb1SSandy Huang V4L2_COLORSPACE_BT2020 = 10, 11479feefb1SSandy Huang 11579feefb1SSandy Huang /* Raw colorspace: for RAW unprocessed images */ 11679feefb1SSandy Huang V4L2_COLORSPACE_RAW = 11, 11779feefb1SSandy Huang 11879feefb1SSandy Huang /* DCI-P3 colorspace, used by cinema projectors */ 11979feefb1SSandy Huang V4L2_COLORSPACE_DCI_P3 = 12, 12079feefb1SSandy Huang }; 12179feefb1SSandy Huang 122*ccd843b9SSandy Huang #define CRTC_INTERLACE_HALVE_V (1 << 0) /* halve V values for interlacing */ 123*ccd843b9SSandy Huang #define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */ 124*ccd843b9SSandy Huang #define CRTC_NO_DBLSCAN (1 << 2) /* don't adjust doublescan */ 125*ccd843b9SSandy Huang #define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */ 126*ccd843b9SSandy Huang #define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | CRTC_NO_VSCAN) 127*ccd843b9SSandy Huang 128*ccd843b9SSandy Huang #define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF 129*ccd843b9SSandy Huang 130b9e63a96SMark Yao struct drm_display_mode { 131b9e63a96SMark Yao /* Proposed mode values */ 132b9e63a96SMark Yao int clock; /* in kHz */ 133b9e63a96SMark Yao int hdisplay; 134b9e63a96SMark Yao int hsync_start; 135b9e63a96SMark Yao int hsync_end; 136b9e63a96SMark Yao int htotal; 137b9e63a96SMark Yao int vdisplay; 138b9e63a96SMark Yao int vsync_start; 139b9e63a96SMark Yao int vsync_end; 140b9e63a96SMark Yao int vtotal; 141b9e63a96SMark Yao int vrefresh; 142b9e63a96SMark Yao int vscan; 143b9e63a96SMark Yao unsigned int flags; 14421016d27SAlgea Cao int picture_aspect_ratio; 145*ccd843b9SSandy Huang int hskew; 146*ccd843b9SSandy Huang unsigned int type; 147*ccd843b9SSandy Huang /* Actual mode we give to hw */ 148*ccd843b9SSandy Huang int crtc_clock; /* in KHz */ 149*ccd843b9SSandy Huang int crtc_hdisplay; 150*ccd843b9SSandy Huang int crtc_hblank_start; 151*ccd843b9SSandy Huang int crtc_hblank_end; 152*ccd843b9SSandy Huang int crtc_hsync_start; 153*ccd843b9SSandy Huang int crtc_hsync_end; 154*ccd843b9SSandy Huang int crtc_htotal; 155*ccd843b9SSandy Huang int crtc_hskew; 156*ccd843b9SSandy Huang int crtc_vdisplay; 157*ccd843b9SSandy Huang int crtc_vblank_start; 158*ccd843b9SSandy Huang int crtc_vblank_end; 159*ccd843b9SSandy Huang int crtc_vsync_start; 160*ccd843b9SSandy Huang int crtc_vsync_end; 161*ccd843b9SSandy Huang int crtc_vtotal; 162b9e63a96SMark Yao }; 163b9e63a96SMark Yao 164b9e63a96SMark Yao #endif 165