xref: /rk3399_rockchip-uboot/include/drm_modes.h (revision a265befef37b147d4bcf05fc84500fe072a3f33f)
1b9e63a96SMark Yao /*
2b9e63a96SMark Yao  * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
3b9e63a96SMark Yao  *
4b9e63a96SMark Yao  * SPDX-License-Identifier:	GPL-2.0+
5b9e63a96SMark Yao  */
6b9e63a96SMark Yao 
7b9e63a96SMark Yao #ifndef _DRM_MODES_H
8b9e63a96SMark Yao #define _DRM_MODES_H
9b9e63a96SMark Yao 
102cb51333SDamon Ding #include "fdtdec.h"
112cb51333SDamon Ding 
12ccd843b9SSandy Huang #define DRM_DISPLAY_INFO_LEN	32
13ccd843b9SSandy Huang #define DRM_CONNECTOR_NAME_LEN	32
14ccd843b9SSandy Huang #define DRM_DISPLAY_MODE_LEN	32
15ccd843b9SSandy Huang #define DRM_PROP_NAME_LEN	32
16ccd843b9SSandy Huang 
17ccd843b9SSandy Huang #define DRM_MODE_TYPE_BUILTIN	(1<<0)
18ccd843b9SSandy Huang #define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
19ccd843b9SSandy Huang #define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
20ccd843b9SSandy Huang #define DRM_MODE_TYPE_PREFERRED	(1<<3)
21ccd843b9SSandy Huang #define DRM_MODE_TYPE_DEFAULT	(1<<4)
22ccd843b9SSandy Huang #define DRM_MODE_TYPE_USERDEF	(1<<5)
23ccd843b9SSandy Huang #define DRM_MODE_TYPE_DRIVER	(1<<6)
2421016d27SAlgea Cao 
25b9e63a96SMark Yao /* Video mode flags */
26b9e63a96SMark Yao /* bit compatible with the xorg definitions. */
27b9e63a96SMark Yao #define DRM_MODE_FLAG_PHSYNC			(1 << 0)
28b9e63a96SMark Yao #define DRM_MODE_FLAG_NHSYNC			(1 << 1)
29b9e63a96SMark Yao #define DRM_MODE_FLAG_PVSYNC			(1 << 2)
30b9e63a96SMark Yao #define DRM_MODE_FLAG_NVSYNC			(1 << 3)
31b9e63a96SMark Yao #define DRM_MODE_FLAG_INTERLACE			(1 << 4)
32b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLSCAN			(1 << 5)
33b9e63a96SMark Yao #define DRM_MODE_FLAG_CSYNC			(1 << 6)
34b9e63a96SMark Yao #define DRM_MODE_FLAG_PCSYNC			(1 << 7)
35b9e63a96SMark Yao #define DRM_MODE_FLAG_NCSYNC			(1 << 8)
36b9e63a96SMark Yao #define DRM_MODE_FLAG_HSKEW			(1 << 9) /* hskew provided */
37b9e63a96SMark Yao #define DRM_MODE_FLAG_BCAST			(1 << 10)
38b9e63a96SMark Yao #define DRM_MODE_FLAG_PIXMUX			(1 << 11)
39b9e63a96SMark Yao #define DRM_MODE_FLAG_DBLCLK			(1 << 12)
40b9e63a96SMark Yao #define DRM_MODE_FLAG_CLKDIV2			(1 << 13)
418e2bab3fSAlgea Cao #define DRM_MODE_FLAG_PPIXDATA			BIT(31)
42e022625eSWyon Bi /*
43e022625eSWyon Bi  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
44e022625eSWyon Bi  * (define not exposed to user space).
45e022625eSWyon Bi  */
46e022625eSWyon Bi #define DRM_MODE_FLAG_3D_MASK			(0x1f << 14)
47e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_NONE			(0 << 14)
48e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1 << 14)
49e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2 << 14)
50e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3 << 14)
51e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4 << 14)
52e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_L_DEPTH		(5 << 14)
53e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6 << 14)
54e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7 << 14)
55e022625eSWyon Bi #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8 << 14)
56b9e63a96SMark Yao 
57ffa55e18SShixiang Zheng /* Panel Mirror control */
58ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_XMIRROR			(1<<28)
59ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_YMIRROR			(1<<29)
60ffa55e18SShixiang Zheng #define DRM_MODE_FLAG_XYMIRROR			(DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR)
6194d85f7bSSandy Huang 
6294d85f7bSSandy Huang /* Picture aspect ratio options */
6394d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_NONE		0
6494d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_4_3		1
6594d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_16_9		2
6694d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_64_27		3
6794d85f7bSSandy Huang #define DRM_MODE_PICTURE_ASPECT_256_135		4
6894d85f7bSSandy Huang 
6994d85f7bSSandy Huang /* Aspect ratio flag bitmask (4 bits 22:19) */
7094d85f7bSSandy Huang #define DRM_MODE_FLAG_PIC_AR_MASK		(0x0F << 19)
7194d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_NONE \
7294d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_NONE << 19)
7394d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_4_3 \
7494d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_4_3 << 19)
7594d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_16_9 \
7694d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_16_9 << 19)
7794d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_64_27 \
7894d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_64_27 << 19)
7994d85f7bSSandy Huang #define  DRM_MODE_FLAG_PIC_AR_256_135 \
8094d85f7bSSandy Huang 			(DRM_MODE_PICTURE_ASPECT_256_135 << 19)
81ffa55e18SShixiang Zheng 
82b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Unknown	0
83b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VGA		1
84b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVII		2
85b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVID		3
86b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DVIA		4
87b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Composite	5
88b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_SVIDEO	6
89b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_LVDS		7
90b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_Component	8
91b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_9PinDIN	9
92b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DisplayPort	10
93b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIA	11
94b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_HDMIB	12
95b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_TV		13
96b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_eDP		14
97b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_VIRTUAL      15
98b9e63a96SMark Yao #define DRM_MODE_CONNECTOR_DSI		16
99ecc31b6eSAndy Yan #define DRM_MODE_CONNECTOR_DPI		17
100b9e63a96SMark Yao 
101b9e63a96SMark Yao #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
102b9e63a96SMark Yao #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
103b9e63a96SMark Yao #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
104b9e63a96SMark Yao #define DRM_EDID_PT_STEREO         (1 << 5)
105b9e63a96SMark Yao #define DRM_EDID_PT_INTERLACED     (1 << 7)
106b9e63a96SMark Yao 
10779feefb1SSandy Huang /* see also http://vektor.theorem.ca/graphics/ycbcr/ */
10879feefb1SSandy Huang enum v4l2_colorspace {
10979feefb1SSandy Huang 	/*
11079feefb1SSandy Huang 	 * Default colorspace, i.e. let the driver figure it out.
11179feefb1SSandy Huang 	 * Can only be used with video capture.
11279feefb1SSandy Huang 	 */
11379feefb1SSandy Huang 	V4L2_COLORSPACE_DEFAULT       = 0,
11479feefb1SSandy Huang 
11579feefb1SSandy Huang 	/* SMPTE 170M: used for broadcast NTSC/PAL SDTV */
11679feefb1SSandy Huang 	V4L2_COLORSPACE_SMPTE170M     = 1,
11779feefb1SSandy Huang 
11879feefb1SSandy Huang 	/* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
11979feefb1SSandy Huang 	V4L2_COLORSPACE_SMPTE240M     = 2,
12079feefb1SSandy Huang 
12179feefb1SSandy Huang 	/* Rec.709: used for HDTV */
12279feefb1SSandy Huang 	V4L2_COLORSPACE_REC709        = 3,
12379feefb1SSandy Huang 
12479feefb1SSandy Huang 	/*
12579feefb1SSandy Huang 	 * Deprecated, do not use. No driver will ever return this. This was
12679feefb1SSandy Huang 	 * based on a misunderstanding of the bt878 datasheet.
12779feefb1SSandy Huang 	 */
12879feefb1SSandy Huang 	V4L2_COLORSPACE_BT878         = 4,
12979feefb1SSandy Huang 
13079feefb1SSandy Huang 	/*
13179feefb1SSandy Huang 	 * NTSC 1953 colorspace. This only makes sense when dealing with
13279feefb1SSandy Huang 	 * really, really old NTSC recordings. Superseded by SMPTE 170M.
13379feefb1SSandy Huang 	 */
13479feefb1SSandy Huang 	V4L2_COLORSPACE_470_SYSTEM_M  = 5,
13579feefb1SSandy Huang 
13679feefb1SSandy Huang 	/*
13779feefb1SSandy Huang 	 * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when
13879feefb1SSandy Huang 	 * dealing with really old PAL/SECAM recordings. Superseded by
13979feefb1SSandy Huang 	 * SMPTE 170M.
14079feefb1SSandy Huang 	 */
14179feefb1SSandy Huang 	V4L2_COLORSPACE_470_SYSTEM_BG = 6,
14279feefb1SSandy Huang 
14379feefb1SSandy Huang 	/*
14479feefb1SSandy Huang 	 * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601
14579feefb1SSandy Huang 	 * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG.
14679feefb1SSandy Huang 	 */
14779feefb1SSandy Huang 	V4L2_COLORSPACE_JPEG          = 7,
14879feefb1SSandy Huang 
14979feefb1SSandy Huang 	/* For RGB colorspaces such as produces by most webcams. */
15079feefb1SSandy Huang 	V4L2_COLORSPACE_SRGB          = 8,
15179feefb1SSandy Huang 
15279feefb1SSandy Huang 	/* AdobeRGB colorspace */
15379feefb1SSandy Huang 	V4L2_COLORSPACE_ADOBERGB      = 9,
15479feefb1SSandy Huang 
15579feefb1SSandy Huang 	/* BT.2020 colorspace, used for UHDTV. */
15679feefb1SSandy Huang 	V4L2_COLORSPACE_BT2020        = 10,
15779feefb1SSandy Huang 
15879feefb1SSandy Huang 	/* Raw colorspace: for RAW unprocessed images */
15979feefb1SSandy Huang 	V4L2_COLORSPACE_RAW           = 11,
16079feefb1SSandy Huang 
16179feefb1SSandy Huang 	/* DCI-P3 colorspace, used by cinema projectors */
16279feefb1SSandy Huang 	V4L2_COLORSPACE_DCI_P3        = 12,
16379feefb1SSandy Huang };
16479feefb1SSandy Huang 
165ccd843b9SSandy Huang #define CRTC_INTERLACE_HALVE_V	(1 << 0) /* halve V values for interlacing */
166ccd843b9SSandy Huang #define CRTC_STEREO_DOUBLE	(1 << 1) /* adjust timings for stereo modes */
167ccd843b9SSandy Huang #define CRTC_NO_DBLSCAN		(1 << 2) /* don't adjust doublescan */
168ccd843b9SSandy Huang #define CRTC_NO_VSCAN		(1 << 3) /* don't adjust doublescan */
1698e2bab3fSAlgea Cao #define CRTC_STEREO_DOUBLE_ONLY	(CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \
1708e2bab3fSAlgea Cao 				 CRTC_NO_VSCAN)
171ccd843b9SSandy Huang 
172ccd843b9SSandy Huang #define DRM_MODE_FLAG_3D_MAX	DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
173ccd843b9SSandy Huang 
174e022625eSWyon Bi #define DRM_MODE_MATCH_TIMINGS		(1 << 0)
175e022625eSWyon Bi #define DRM_MODE_MATCH_CLOCK		(1 << 1)
176e022625eSWyon Bi #define DRM_MODE_MATCH_FLAGS		(1 << 2)
177e022625eSWyon Bi #define DRM_MODE_MATCH_3D_FLAGS		(1 << 3)
178e022625eSWyon Bi #define DRM_MODE_MATCH_ASPECT_RATIO	(1 << 4)
179e022625eSWyon Bi 
180b9e63a96SMark Yao struct drm_display_mode {
181b9e63a96SMark Yao 	/* Proposed mode values */
182b9e63a96SMark Yao 	int clock;		/* in kHz */
183b9e63a96SMark Yao 	int hdisplay;
184b9e63a96SMark Yao 	int hsync_start;
185b9e63a96SMark Yao 	int hsync_end;
186b9e63a96SMark Yao 	int htotal;
187b9e63a96SMark Yao 	int vdisplay;
188b9e63a96SMark Yao 	int vsync_start;
189b9e63a96SMark Yao 	int vsync_end;
190b9e63a96SMark Yao 	int vtotal;
191b9e63a96SMark Yao 	int vrefresh;
192b9e63a96SMark Yao 	int vscan;
193b9e63a96SMark Yao 	unsigned int flags;
19421016d27SAlgea Cao 	int picture_aspect_ratio;
195ccd843b9SSandy Huang 	int hskew;
196ccd843b9SSandy Huang 	unsigned int type;
197ccd843b9SSandy Huang 	/* Actual mode we give to hw */
198ccd843b9SSandy Huang 	int crtc_clock;         /* in KHz */
199ccd843b9SSandy Huang 	int crtc_hdisplay;
200ccd843b9SSandy Huang 	int crtc_hblank_start;
201ccd843b9SSandy Huang 	int crtc_hblank_end;
202ccd843b9SSandy Huang 	int crtc_hsync_start;
203ccd843b9SSandy Huang 	int crtc_hsync_end;
204ccd843b9SSandy Huang 	int crtc_htotal;
205ccd843b9SSandy Huang 	int crtc_hskew;
206ccd843b9SSandy Huang 	int crtc_vdisplay;
207ccd843b9SSandy Huang 	int crtc_vblank_start;
208ccd843b9SSandy Huang 	int crtc_vblank_end;
209ccd843b9SSandy Huang 	int crtc_vsync_start;
210ccd843b9SSandy Huang 	int crtc_vsync_end;
211ccd843b9SSandy Huang 	int crtc_vtotal;
2128e2bab3fSAlgea Cao 	bool invalid;
213b9e63a96SMark Yao };
214b9e63a96SMark Yao 
215*a265befeSGuochun Huang /**
216*a265befeSGuochun Huang  * enum drm_mode_status - hardware support status of a mode
217*a265befeSGuochun Huang  * @MODE_OK: Mode OK
218*a265befeSGuochun Huang  * @MODE_HSYNC: hsync out of range
219*a265befeSGuochun Huang  * @MODE_VSYNC: vsync out of range
220*a265befeSGuochun Huang  * @MODE_H_ILLEGAL: mode has illegal horizontal timings
221*a265befeSGuochun Huang  * @MODE_V_ILLEGAL: mode has illegal vertical timings
222*a265befeSGuochun Huang  * @MODE_BAD_WIDTH: requires an unsupported linepitch
223*a265befeSGuochun Huang  * @MODE_NOMODE: no mode with a matching name
224*a265befeSGuochun Huang  * @MODE_NO_INTERLACE: interlaced mode not supported
225*a265befeSGuochun Huang  * @MODE_NO_DBLESCAN: doublescan mode not supported
226*a265befeSGuochun Huang  * @MODE_NO_VSCAN: multiscan mode not supported
227*a265befeSGuochun Huang  * @MODE_MEM: insufficient video memory
228*a265befeSGuochun Huang  * @MODE_VIRTUAL_X: mode width too large for specified virtual size
229*a265befeSGuochun Huang  * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
230*a265befeSGuochun Huang  * @MODE_MEM_VIRT: insufficient video memory given virtual size
231*a265befeSGuochun Huang  * @MODE_NOCLOCK: no fixed clock available
232*a265befeSGuochun Huang  * @MODE_CLOCK_HIGH: clock required is too high
233*a265befeSGuochun Huang  * @MODE_CLOCK_LOW: clock required is too low
234*a265befeSGuochun Huang  * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
235*a265befeSGuochun Huang  * @MODE_BAD_HVALUE: horizontal timing was out of range
236*a265befeSGuochun Huang  * @MODE_BAD_VVALUE: vertical timing was out of range
237*a265befeSGuochun Huang  * @MODE_BAD_VSCAN: VScan value out of range
238*a265befeSGuochun Huang  * @MODE_HSYNC_NARROW: horizontal sync too narrow
239*a265befeSGuochun Huang  * @MODE_HSYNC_WIDE: horizontal sync too wide
240*a265befeSGuochun Huang  * @MODE_HBLANK_NARROW: horizontal blanking too narrow
241*a265befeSGuochun Huang  * @MODE_HBLANK_WIDE: horizontal blanking too wide
242*a265befeSGuochun Huang  * @MODE_VSYNC_NARROW: vertical sync too narrow
243*a265befeSGuochun Huang  * @MODE_VSYNC_WIDE: vertical sync too wide
244*a265befeSGuochun Huang  * @MODE_VBLANK_NARROW: vertical blanking too narrow
245*a265befeSGuochun Huang  * @MODE_VBLANK_WIDE: vertical blanking too wide
246*a265befeSGuochun Huang  * @MODE_PANEL: exceeds panel dimensions
247*a265befeSGuochun Huang  * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
248*a265befeSGuochun Huang  * @MODE_ONE_WIDTH: only one width is supported
249*a265befeSGuochun Huang  * @MODE_ONE_HEIGHT: only one height is supported
250*a265befeSGuochun Huang  * @MODE_ONE_SIZE: only one resolution is supported
251*a265befeSGuochun Huang  * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
252*a265befeSGuochun Huang  * @MODE_NO_STEREO: stereo modes not supported
253*a265befeSGuochun Huang  * @MODE_NO_420: ycbcr 420 modes not supported
254*a265befeSGuochun Huang  * @MODE_STALE: mode has become stale
255*a265befeSGuochun Huang  * @MODE_BAD: unspecified reason
256*a265befeSGuochun Huang  * @MODE_ERROR: error condition
257*a265befeSGuochun Huang  *
258*a265befeSGuochun Huang  * This enum is used to filter out modes not supported by the driver/hardware
259*a265befeSGuochun Huang  * combination.
260*a265befeSGuochun Huang  */
261*a265befeSGuochun Huang enum drm_mode_status {
262*a265befeSGuochun Huang 	MODE_OK = 0,
263*a265befeSGuochun Huang 	MODE_HSYNC,
264*a265befeSGuochun Huang 	MODE_VSYNC,
265*a265befeSGuochun Huang 	MODE_H_ILLEGAL,
266*a265befeSGuochun Huang 	MODE_V_ILLEGAL,
267*a265befeSGuochun Huang 	MODE_BAD_WIDTH,
268*a265befeSGuochun Huang 	MODE_NOMODE,
269*a265befeSGuochun Huang 	MODE_NO_INTERLACE,
270*a265befeSGuochun Huang 	MODE_NO_DBLESCAN,
271*a265befeSGuochun Huang 	MODE_NO_VSCAN,
272*a265befeSGuochun Huang 	MODE_MEM,
273*a265befeSGuochun Huang 	MODE_VIRTUAL_X,
274*a265befeSGuochun Huang 	MODE_VIRTUAL_Y,
275*a265befeSGuochun Huang 	MODE_MEM_VIRT,
276*a265befeSGuochun Huang 	MODE_NOCLOCK,
277*a265befeSGuochun Huang 	MODE_CLOCK_HIGH,
278*a265befeSGuochun Huang 	MODE_CLOCK_LOW,
279*a265befeSGuochun Huang 	MODE_CLOCK_RANGE,
280*a265befeSGuochun Huang 	MODE_BAD_HVALUE,
281*a265befeSGuochun Huang 	MODE_BAD_VVALUE,
282*a265befeSGuochun Huang 	MODE_BAD_VSCAN,
283*a265befeSGuochun Huang 	MODE_HSYNC_NARROW,
284*a265befeSGuochun Huang 	MODE_HSYNC_WIDE,
285*a265befeSGuochun Huang 	MODE_HBLANK_NARROW,
286*a265befeSGuochun Huang 	MODE_HBLANK_WIDE,
287*a265befeSGuochun Huang 	MODE_VSYNC_NARROW,
288*a265befeSGuochun Huang 	MODE_VSYNC_WIDE,
289*a265befeSGuochun Huang 	MODE_VBLANK_NARROW,
290*a265befeSGuochun Huang 	MODE_VBLANK_WIDE,
291*a265befeSGuochun Huang 	MODE_PANEL,
292*a265befeSGuochun Huang 	MODE_INTERLACE_WIDTH,
293*a265befeSGuochun Huang 	MODE_ONE_WIDTH,
294*a265befeSGuochun Huang 	MODE_ONE_HEIGHT,
295*a265befeSGuochun Huang 	MODE_ONE_SIZE,
296*a265befeSGuochun Huang 	MODE_NO_REDUCED,
297*a265befeSGuochun Huang 	MODE_NO_STEREO,
298*a265befeSGuochun Huang 	MODE_NO_420,
299*a265befeSGuochun Huang 	MODE_STALE = -3,
300*a265befeSGuochun Huang 	MODE_BAD = -2,
301*a265befeSGuochun Huang 	MODE_ERROR = -1
302*a265befeSGuochun Huang };
303*a265befeSGuochun Huang 
3042cb51333SDamon Ding /*
3052cb51333SDamon Ding  * Subsystem independent description of a videomode.
3062cb51333SDamon Ding  * Can be generated from struct display_timing.
3072cb51333SDamon Ding  */
3082cb51333SDamon Ding struct videomode {
3092cb51333SDamon Ding 	unsigned long pixelclock;	/* pixelclock in Hz */
3102cb51333SDamon Ding 
3112cb51333SDamon Ding 	u32 hactive;
3122cb51333SDamon Ding 	u32 hfront_porch;
3132cb51333SDamon Ding 	u32 hback_porch;
3142cb51333SDamon Ding 	u32 hsync_len;
3152cb51333SDamon Ding 
3162cb51333SDamon Ding 	u32 vactive;
3172cb51333SDamon Ding 	u32 vfront_porch;
3182cb51333SDamon Ding 	u32 vback_porch;
3192cb51333SDamon Ding 	u32 vsync_len;
3202cb51333SDamon Ding 
3212cb51333SDamon Ding 	enum display_flags flags; /* display flags */
3222cb51333SDamon Ding };
3232cb51333SDamon Ding 
324e022625eSWyon Bi struct drm_display_mode *drm_mode_create(void);
325*a265befeSGuochun Huang void drm_mode_copy(struct drm_display_mode *dst,
326*a265befeSGuochun Huang 		   const struct drm_display_mode *src);
327e022625eSWyon Bi void drm_mode_destroy(struct drm_display_mode *mode);
328e022625eSWyon Bi bool drm_mode_match(const struct drm_display_mode *mode1,
329e022625eSWyon Bi 		    const struct drm_display_mode *mode2,
330e022625eSWyon Bi 		    unsigned int match_flags);
331e022625eSWyon Bi bool drm_mode_equal(const struct drm_display_mode *mode1,
332e022625eSWyon Bi 		    const struct drm_display_mode *mode2);
333*a265befeSGuochun Huang void drm_display_mode_from_videomode(const struct videomode *vm,
334*a265befeSGuochun Huang 				     struct drm_display_mode *dmode);
3352cb51333SDamon Ding void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
3362cb51333SDamon Ding 				   struct videomode *vm);
337e022625eSWyon Bi 
338b9e63a96SMark Yao #endif
339