1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright © 2008 Keith Packard 4 * 5 * Permission to use, copy, modify, distribute, and sell this software and its 6 * documentation for any purpose is hereby granted without fee, provided that 7 * the above copyright notice appear in all copies and that both that copyright 8 * notice and this permission notice appear in supporting documentation, and 9 * that the name of the copyright holders not be used in advertising or 10 * publicity pertaining to distribution of the software without specific, 11 * written prior permission. The copyright holders make no representations 12 * about the suitability of this software for any purpose. It is provided "as 13 * is" without express or implied warranty. 14 * 15 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 16 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 17 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 19 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 20 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 21 * OF THIS SOFTWARE. 22 */ 23 24 #ifndef _DRM_DP_HELPER_H_ 25 #define _DRM_DP_HELPER_H_ 26 27 /* 28 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 29 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 30 * 1.0 devices basically don't exist in the wild. 31 * 32 * Abbreviations, in chronological order: 33 * 34 * eDP: Embedded DisplayPort version 1 35 * DPI: DisplayPort Interoperability Guideline v1.1a 36 * 1.2: DisplayPort 1.2 37 * MST: Multistream Transport - part of DP 1.2a 38 * 39 * 1.2 formally includes both eDP and DPI definitions. 40 */ 41 42 #define DP_AUX_MAX_PAYLOAD_BYTES 16 43 44 #define DP_AUX_I2C_WRITE 0x0 45 #define DP_AUX_I2C_READ 0x1 46 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 47 #define DP_AUX_I2C_MOT 0x4 48 #define DP_AUX_NATIVE_WRITE 0x8 49 #define DP_AUX_NATIVE_READ 0x9 50 51 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 52 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 53 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 54 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 55 56 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 57 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 58 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 59 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 60 61 /* AUX CH addresses */ 62 /* DPCD */ 63 #define DP_DPCD_REV 0x000 64 # define DP_DPCD_REV_10 0x10 65 # define DP_DPCD_REV_11 0x11 66 # define DP_DPCD_REV_12 0x12 67 # define DP_DPCD_REV_13 0x13 68 # define DP_DPCD_REV_14 0x14 69 70 #define DP_MAX_LINK_RATE 0x001 71 72 #define DP_MAX_LANE_COUNT 0x002 73 # define DP_MAX_LANE_COUNT_MASK 0x1f 74 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 75 # define DP_ENHANCED_FRAME_CAP (1 << 7) 76 77 #define DP_MAX_DOWNSPREAD 0x003 78 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) 79 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 80 # define DP_TPS4_SUPPORTED (1 << 7) 81 82 #define DP_NORP 0x004 83 84 #define DP_DOWNSTREAMPORT_PRESENT 0x005 85 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 86 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 87 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 88 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 89 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 90 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 91 # define DP_FORMAT_CONVERSION (1 << 3) 92 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 93 94 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 95 96 #define DP_DOWN_STREAM_PORT_COUNT 0x007 97 # define DP_PORT_COUNT_MASK 0x0f 98 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 99 # define DP_OUI_SUPPORT (1 << 7) 100 101 #define DP_RECEIVE_PORT_0_CAP_0 0x008 102 # define DP_LOCAL_EDID_PRESENT (1 << 1) 103 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 104 105 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 106 107 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 108 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 109 110 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 111 # define DP_I2C_SPEED_1K 0x01 112 # define DP_I2C_SPEED_5K 0x02 113 # define DP_I2C_SPEED_10K 0x04 114 # define DP_I2C_SPEED_100K 0x08 115 # define DP_I2C_SPEED_400K 0x10 116 # define DP_I2C_SPEED_1M 0x20 117 118 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 119 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 120 # define DP_FRAMING_CHANGE_CAP (1 << 1) 121 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 122 123 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 124 # define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */ 125 126 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 127 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 128 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 129 130 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 131 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 132 133 /* Multiple stream transport */ 134 #define DP_FAUX_CAP 0x020 /* 1.2 */ 135 # define DP_FAUX_CAP_1 (1 << 0) 136 137 #define DP_MSTM_CAP 0x021 /* 1.2 */ 138 # define DP_MST_CAP (1 << 0) 139 140 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 141 142 /* AV_SYNC_DATA_BLOCK 1.2 */ 143 #define DP_AV_GRANULARITY 0x023 144 # define DP_AG_FACTOR_MASK (0xf << 0) 145 # define DP_AG_FACTOR_3MS (0 << 0) 146 # define DP_AG_FACTOR_2MS (1 << 0) 147 # define DP_AG_FACTOR_1MS (2 << 0) 148 # define DP_AG_FACTOR_500US (3 << 0) 149 # define DP_AG_FACTOR_200US (4 << 0) 150 # define DP_AG_FACTOR_100US (5 << 0) 151 # define DP_AG_FACTOR_10US (6 << 0) 152 # define DP_AG_FACTOR_1US (7 << 0) 153 # define DP_VG_FACTOR_MASK (0xf << 4) 154 # define DP_VG_FACTOR_3MS (0 << 4) 155 # define DP_VG_FACTOR_2MS (1 << 4) 156 # define DP_VG_FACTOR_1MS (2 << 4) 157 # define DP_VG_FACTOR_500US (3 << 4) 158 # define DP_VG_FACTOR_200US (4 << 4) 159 # define DP_VG_FACTOR_100US (5 << 4) 160 161 #define DP_AUD_DEC_LAT0 0x024 162 #define DP_AUD_DEC_LAT1 0x025 163 164 #define DP_AUD_PP_LAT0 0x026 165 #define DP_AUD_PP_LAT1 0x027 166 167 #define DP_VID_INTER_LAT 0x028 168 169 #define DP_VID_PROG_LAT 0x029 170 171 #define DP_REP_LAT 0x02a 172 173 #define DP_AUD_DEL_INS0 0x02b 174 #define DP_AUD_DEL_INS1 0x02c 175 #define DP_AUD_DEL_INS2 0x02d 176 /* End of AV_SYNC_DATA_BLOCK */ 177 178 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 179 # define DP_ALPM_CAP (1 << 0) 180 181 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 182 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 183 184 #define DP_GUID 0x030 /* 1.2 */ 185 186 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ 187 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) 188 189 #define DP_DSC_REV 0x061 190 # define DP_DSC_MAJOR_MASK (0xf << 0) 191 # define DP_DSC_MINOR_MASK (0xf << 4) 192 # define DP_DSC_MAJOR_SHIFT 0 193 # define DP_DSC_MINOR_SHIFT 4 194 195 #define DP_DSC_RC_BUF_BLK_SIZE 0x062 196 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 197 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 198 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 199 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 200 201 #define DP_DSC_RC_BUF_SIZE 0x063 202 203 #define DP_DSC_SLICE_CAP_1 0x064 204 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) 205 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) 206 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) 207 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) 208 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) 209 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) 210 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) 211 212 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 213 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) 214 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 215 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 216 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 217 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 218 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 219 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 220 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 221 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 222 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 223 224 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 225 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) 226 227 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ 228 229 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ 230 231 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 232 # define DP_DSC_RGB (1 << 0) 233 # define DP_DSC_YCbCr444 (1 << 1) 234 # define DP_DSC_YCbCr422_Simple (1 << 2) 235 # define DP_DSC_YCbCr422_Native (1 << 3) 236 # define DP_DSC_YCbCr420_Native (1 << 4) 237 238 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A 239 # define DP_DSC_8_BPC (1 << 1) 240 # define DP_DSC_10_BPC (1 << 2) 241 # define DP_DSC_12_BPC (1 << 3) 242 243 #define DP_DSC_PEAK_THROUGHPUT 0x06B 244 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) 245 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 246 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) 247 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) 248 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) 249 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) 250 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) 251 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) 252 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) 253 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) 254 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) 255 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) 256 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) 257 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) 258 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) 259 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) 260 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) 261 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 262 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) 263 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) 264 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) 265 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) 266 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) 267 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) 268 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) 269 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) 270 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) 271 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) 272 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) 273 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) 274 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) 275 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) 276 277 #define DP_DSC_MAX_SLICE_WIDTH 0x06C 278 279 #define DP_DSC_SLICE_CAP_2 0x06D 280 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) 281 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) 282 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) 283 284 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F 285 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 286 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 287 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 288 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 289 # define DP_DSC_BITS_PER_PIXEL_1 0x4 290 291 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 292 # define DP_PSR_IS_SUPPORTED 1 293 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 294 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ 295 296 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 297 # define DP_PSR_NO_TRAIN_ON_EXIT 1 298 # define DP_PSR_SETUP_TIME_330 (0 << 1) 299 # define DP_PSR_SETUP_TIME_275 (1 << 1) 300 # define DP_PSR_SETUP_TIME_220 (2 << 1) 301 # define DP_PSR_SETUP_TIME_165 (3 << 1) 302 # define DP_PSR_SETUP_TIME_110 (4 << 1) 303 # define DP_PSR_SETUP_TIME_55 (5 << 1) 304 # define DP_PSR_SETUP_TIME_0 (6 << 1) 305 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 306 # define DP_PSR_SETUP_TIME_SHIFT 1 307 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ 308 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ 309 /* 310 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 311 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 312 * each port's descriptor is one byte wide. If it was set, each port's is 313 * four bytes wide, starting with the one byte from the base info. As of 314 * DP interop v1.1a only VGA defines additional detail. 315 */ 316 317 /* offset 0 */ 318 #define DP_DOWNSTREAM_PORT_0 0x80 319 # define DP_DS_PORT_TYPE_MASK (7 << 0) 320 # define DP_DS_PORT_TYPE_DP 0 321 # define DP_DS_PORT_TYPE_VGA 1 322 # define DP_DS_PORT_TYPE_DVI 2 323 # define DP_DS_PORT_TYPE_HDMI 3 324 # define DP_DS_PORT_TYPE_NON_EDID 4 325 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 326 # define DP_DS_PORT_TYPE_WIRELESS 6 327 # define DP_DS_PORT_HPD (1 << 3) 328 /* offset 1 for VGA is maximum megapixels per second / 8 */ 329 /* offset 2 */ 330 # define DP_DS_MAX_BPC_MASK (3 << 0) 331 # define DP_DS_8BPC 0 332 # define DP_DS_10BPC 1 333 # define DP_DS_12BPC 2 334 # define DP_DS_16BPC 3 335 336 /* DP Forward error Correction Registers */ 337 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */ 338 # define DP_FEC_CAPABLE (1 << 0) 339 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) 340 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) 341 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) 342 343 /* link configuration */ 344 #define DP_LINK_BW_SET 0x100 345 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 346 # define DP_LINK_BW_1_62 0x06 347 # define DP_LINK_BW_2_7 0x0a 348 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 349 # define DP_LINK_BW_8_1 0x1e /* 1.4 */ 350 351 #define DP_LANE_COUNT_SET 0x101 352 # define DP_LANE_COUNT_MASK 0x0f 353 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 354 355 #define DP_TRAINING_PATTERN_SET 0x102 356 # define DP_TRAINING_PATTERN_DISABLE 0 357 # define DP_TRAINING_PATTERN_1 1 358 # define DP_TRAINING_PATTERN_2 2 359 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 360 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */ 361 # define DP_TRAINING_PATTERN_MASK 0x3 362 # define DP_TRAINING_PATTERN_MASK_1_4 0xf 363 364 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 365 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 366 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 367 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 368 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 369 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 370 371 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 372 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 373 374 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 375 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 376 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 377 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 378 379 #define DP_TRAINING_LANE0_SET 0x103 380 #define DP_TRAINING_LANE1_SET 0x104 381 #define DP_TRAINING_LANE2_SET 0x105 382 #define DP_TRAINING_LANE3_SET 0x106 383 384 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 385 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 386 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 387 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 388 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 389 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 390 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 391 392 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 393 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 394 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 395 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 396 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 397 398 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 399 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 400 401 #define DP_DOWNSPREAD_CTRL 0x107 402 # define DP_SPREAD_AMP_0_5 (1 << 4) 403 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 404 405 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 406 # define DP_SET_ANSI_8B10B (1 << 0) 407 408 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 409 /* bitmask as for DP_I2C_SPEED_CAP */ 410 411 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 412 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 413 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 414 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 415 416 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 417 #define DP_LINK_QUAL_LANE1_SET 0x10c 418 #define DP_LINK_QUAL_LANE2_SET 0x10d 419 #define DP_LINK_QUAL_LANE3_SET 0x10e 420 # define DP_LINK_QUAL_PATTERN_DISABLE 0 421 # define DP_LINK_QUAL_PATTERN_D10_2 1 422 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 423 # define DP_LINK_QUAL_PATTERN_PRBS7 3 424 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 425 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 426 # define DP_LINK_QUAL_PATTERN_MASK 7 427 428 #define DP_TRAINING_LANE0_1_SET2 0x10f 429 #define DP_TRAINING_LANE2_3_SET2 0x110 430 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 431 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 432 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 433 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 434 435 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 436 # define DP_MST_EN (1 << 0) 437 # define DP_UP_REQ_EN (1 << 1) 438 # define DP_UPSTREAM_IS_SRC (1 << 2) 439 440 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 441 #define DP_AUDIO_DELAY1 0x113 442 #define DP_AUDIO_DELAY2 0x114 443 444 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 445 # define DP_LINK_RATE_SET_SHIFT 0 446 # define DP_LINK_RATE_SET_MASK (7 << 0) 447 448 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 449 # define DP_ALPM_ENABLE (1 << 0) 450 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 451 452 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 453 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 454 # define DP_IRQ_HPD_ENABLE (1 << 1) 455 456 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 457 # define DP_PWR_NOT_NEEDED (1 << 0) 458 459 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ 460 # define DP_FEC_READY (1 << 0) 461 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) 462 # define DP_FEC_ERR_COUNT_DIS (0 << 1) 463 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) 464 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) 465 # define DP_FEC_BIT_ERROR_COUNT (3 << 1) 466 # define DP_FEC_LANE_SELECT_MASK (3 << 4) 467 # define DP_FEC_LANE_0_SELECT (0 << 4) 468 # define DP_FEC_LANE_1_SELECT (1 << 4) 469 # define DP_FEC_LANE_2_SELECT (2 << 4) 470 # define DP_FEC_LANE_3_SELECT (3 << 4) 471 472 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 473 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 474 475 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ 476 477 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 478 # define DP_PSR_ENABLE (1 << 0) 479 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 480 # define DP_PSR_CRC_VERIFICATION (1 << 2) 481 # define DP_PSR_FRAME_CAPTURE (1 << 3) 482 # define DP_PSR_SELECTIVE_UPDATE (1 << 4) 483 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) 484 # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ 485 486 #define DP_ADAPTER_CTRL 0x1a0 487 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 488 489 #define DP_BRANCH_DEVICE_CTRL 0x1a1 490 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 491 492 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 493 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 494 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 495 496 #define DP_SINK_COUNT 0x200 497 /* prior to 1.2 bit 7 was reserved mbz */ 498 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 499 # define DP_SINK_CP_READY (1 << 6) 500 501 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 502 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 503 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 504 # define DP_CP_IRQ (1 << 2) 505 # define DP_MCCS_IRQ (1 << 3) 506 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 507 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 508 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 509 510 #define DP_LANE0_1_STATUS 0x202 511 #define DP_LANE2_3_STATUS 0x203 512 # define DP_LANE_CR_DONE (1 << 0) 513 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 514 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 515 516 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 517 DP_LANE_CHANNEL_EQ_DONE | \ 518 DP_LANE_SYMBOL_LOCKED) 519 520 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 521 522 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 523 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 524 #define DP_LINK_STATUS_UPDATED (1 << 7) 525 526 #define DP_SINK_STATUS 0x205 527 528 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 529 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 530 531 #define DP_ADJUST_REQUEST_LANE0_1 0x206 532 #define DP_ADJUST_REQUEST_LANE2_3 0x207 533 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 534 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 535 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 536 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 537 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 538 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 539 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 540 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 541 542 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c 543 544 #define DP_TEST_REQUEST 0x218 545 # define DP_TEST_LINK_TRAINING (1 << 0) 546 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 547 # define DP_TEST_LINK_EDID_READ (1 << 2) 548 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 549 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 550 551 #define DP_TEST_LINK_RATE 0x219 552 # define DP_LINK_RATE_162 (0x6) 553 # define DP_LINK_RATE_27 (0xa) 554 555 #define DP_TEST_LANE_COUNT 0x220 556 557 #define DP_TEST_PATTERN 0x221 558 # define DP_NO_TEST_PATTERN 0x0 559 # define DP_COLOR_RAMP 0x1 560 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 561 # define DP_COLOR_SQUARE 0x3 562 563 #define DP_TEST_H_TOTAL_HI 0x222 564 #define DP_TEST_H_TOTAL_LO 0x223 565 566 #define DP_TEST_V_TOTAL_HI 0x224 567 #define DP_TEST_V_TOTAL_LO 0x225 568 569 #define DP_TEST_H_START_HI 0x226 570 #define DP_TEST_H_START_LO 0x227 571 572 #define DP_TEST_V_START_HI 0x228 573 #define DP_TEST_V_START_LO 0x229 574 575 #define DP_TEST_HSYNC_HI 0x22A 576 # define DP_TEST_HSYNC_POLARITY (1 << 7) 577 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) 578 #define DP_TEST_HSYNC_WIDTH_LO 0x22B 579 580 #define DP_TEST_VSYNC_HI 0x22C 581 # define DP_TEST_VSYNC_POLARITY (1 << 7) 582 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) 583 #define DP_TEST_VSYNC_WIDTH_LO 0x22D 584 585 #define DP_TEST_H_WIDTH_HI 0x22E 586 #define DP_TEST_H_WIDTH_LO 0x22F 587 588 #define DP_TEST_V_HEIGHT_HI 0x230 589 #define DP_TEST_V_HEIGHT_LO 0x231 590 591 #define DP_TEST_MISC0 0x232 592 # define DP_TEST_SYNC_CLOCK (1 << 0) 593 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) 594 # define DP_TEST_COLOR_FORMAT_SHIFT 1 595 # define DP_COLOR_FORMAT_RGB (0 << 1) 596 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) 597 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) 598 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) 599 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) 600 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) 601 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) 602 # define DP_TEST_BIT_DEPTH_MASK (7 << 5) 603 # define DP_TEST_BIT_DEPTH_SHIFT 5 604 # define DP_TEST_BIT_DEPTH_6 (0 << 5) 605 # define DP_TEST_BIT_DEPTH_8 (1 << 5) 606 # define DP_TEST_BIT_DEPTH_10 (2 << 5) 607 # define DP_TEST_BIT_DEPTH_12 (3 << 5) 608 # define DP_TEST_BIT_DEPTH_16 (4 << 5) 609 610 #define DP_TEST_MISC1 0x233 611 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) 612 # define DP_TEST_INTERLACED (1 << 1) 613 614 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 615 616 #define DP_TEST_MISC0 0x232 617 618 #define DP_TEST_CRC_R_CR 0x240 619 #define DP_TEST_CRC_G_Y 0x242 620 #define DP_TEST_CRC_B_CB 0x244 621 622 #define DP_TEST_SINK_MISC 0x246 623 # define DP_TEST_CRC_SUPPORTED (1 << 5) 624 # define DP_TEST_COUNT_MASK 0xf 625 626 #define DP_TEST_PHY_PATTERN 0x248 627 # define DP_TEST_PHY_PATTERN_NONE 0x0 628 # define DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING 0x1 629 # define DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT 0x2 630 # define DP_TEST_PHY_PATTERN_PRBS7 0x3 631 # define DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN 0x4 632 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_1 0x5 633 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_2 0x6 634 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_3 0x7 635 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 636 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 637 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 638 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 639 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 640 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 641 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 642 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 643 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 644 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 645 646 #define DP_TEST_RESPONSE 0x260 647 # define DP_TEST_ACK (1 << 0) 648 # define DP_TEST_NAK (1 << 1) 649 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 650 651 #define DP_TEST_EDID_CHECKSUM 0x261 652 653 #define DP_TEST_SINK 0x270 654 # define DP_TEST_SINK_START (1 << 0) 655 656 #define DP_FEC_STATUS 0x280 /* 1.4 */ 657 # define DP_FEC_DECODE_EN_DETECTED (1 << 0) 658 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1) 659 660 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ 661 662 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ 663 # define DP_FEC_ERROR_COUNT_MASK 0x7F 664 # define DP_FEC_ERR_COUNT_VALID (1 << 7) 665 666 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 667 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 668 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 669 670 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 671 /* up to ID_SLOT_63 at 0x2ff */ 672 673 #define DP_SOURCE_OUI 0x300 674 #define DP_SINK_OUI 0x400 675 #define DP_BRANCH_OUI 0x500 676 #define DP_BRANCH_ID 0x503 677 #define DP_BRANCH_REVISION_START 0x509 678 #define DP_BRANCH_HW_REV 0x509 679 #define DP_BRANCH_SW_REV 0x50A 680 681 #define DP_SET_POWER 0x600 682 # define DP_SET_POWER_D0 0x1 683 # define DP_SET_POWER_D3 0x2 684 # define DP_SET_POWER_MASK 0x3 685 # define DP_SET_POWER_D3_AUX_ON 0x5 686 687 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 688 # define DP_EDP_11 0x00 689 # define DP_EDP_12 0x01 690 # define DP_EDP_13 0x02 691 # define DP_EDP_14 0x03 692 693 #define DP_EDP_GENERAL_CAP_1 0x701 694 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 695 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 696 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 697 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 698 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 699 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 700 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 701 # define DP_EDP_SET_POWER_CAP (1 << 7) 702 703 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 704 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 705 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 706 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 707 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 708 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 709 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 710 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 711 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 712 713 #define DP_EDP_GENERAL_CAP_2 0x703 714 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 715 716 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 717 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 718 # define DP_EDP_X_REGION_CAP_SHIFT 0 719 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 720 # define DP_EDP_Y_REGION_CAP_SHIFT 4 721 722 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 723 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 724 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 725 # define DP_EDP_FRC_ENABLE (1 << 2) 726 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 727 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 728 729 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 730 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 731 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 732 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 733 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 734 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 735 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 736 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 737 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 738 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 739 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 740 741 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 742 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 743 744 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 745 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 746 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 747 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) 748 749 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 750 751 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 752 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 753 754 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 755 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 756 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 757 758 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 759 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 760 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 761 762 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 763 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 764 765 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 766 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 767 768 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 769 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 770 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 771 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 772 773 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 774 /* 0-5 sink count */ 775 # define DP_SINK_COUNT_CP_READY (1 << 6) 776 777 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 778 779 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 780 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) 781 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1) 782 # define DP_CEC_IRQ (1 << 2) 783 784 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 785 786 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 787 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 788 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 789 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 790 791 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 792 # define DP_PSR_CAPS_CHANGE (1 << 0) 793 794 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 795 # define DP_PSR_SINK_INACTIVE 0 796 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 797 # define DP_PSR_SINK_ACTIVE_RFB 2 798 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 799 # define DP_PSR_SINK_ACTIVE_RESYNC 4 800 # define DP_PSR_SINK_INTERNAL_ERROR 7 801 # define DP_PSR_SINK_STATE_MASK 0x07 802 803 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ 804 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) 805 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 806 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) 807 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 808 809 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ 810 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ 811 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ 812 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ 813 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */ 814 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ 815 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ 816 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ 817 818 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 819 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 820 821 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ 822 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ 823 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ 824 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ 825 826 #define DP_DP13_DPCD_REV 0x2200 827 #define DP_DP13_MAX_LINK_RATE 0x2201 828 829 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ 830 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ 831 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ 832 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ 833 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ 834 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ 835 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ 836 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ 837 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ 838 839 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ 840 #define DP_CEC_TUNNELING_CAPABILITY 0x3000 841 # define DP_CEC_TUNNELING_CAPABLE (1 << 0) 842 # define DP_CEC_SNOOPING_CAPABLE (1 << 1) 843 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) 844 845 #define DP_CEC_TUNNELING_CONTROL 0x3001 846 # define DP_CEC_TUNNELING_ENABLE (1 << 0) 847 # define DP_CEC_SNOOPING_ENABLE (1 << 1) 848 849 #define DP_CEC_RX_MESSAGE_INFO 0x3002 850 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) 851 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 852 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) 853 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) 854 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6) 855 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7) 856 857 #define DP_CEC_TX_MESSAGE_INFO 0x3003 858 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) 859 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 860 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) 861 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4 862 # define DP_CEC_TX_MESSAGE_SEND (1 << 7) 863 864 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 865 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) 866 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) 867 # define DP_CEC_TX_MESSAGE_SENT (1 << 4) 868 # define DP_CEC_TX_LINE_ERROR (1 << 5) 869 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) 870 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) 871 872 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ 873 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) 874 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) 875 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) 876 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) 877 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) 878 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) 879 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) 880 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) 881 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ 882 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) 883 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) 884 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) 885 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) 886 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) 887 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) 888 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) 889 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) 890 891 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010 892 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 893 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 894 895 #define DP_AUX_HDCP_BKSV 0x68000 896 #define DP_AUX_HDCP_RI_PRIME 0x68005 897 #define DP_AUX_HDCP_AKSV 0x68007 898 #define DP_AUX_HDCP_AN 0x6800C 899 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + (h) * 4) 900 #define DP_AUX_HDCP_BCAPS 0x68028 901 # define DP_BCAPS_REPEATER_PRESENT BIT(1) 902 # define DP_BCAPS_HDCP_CAPABLE BIT(0) 903 #define DP_AUX_HDCP_BSTATUS 0x68029 904 # define DP_BSTATUS_REAUTH_REQ BIT(3) 905 # define DP_BSTATUS_LINK_FAILURE BIT(2) 906 # define DP_BSTATUS_R0_PRIME_READY BIT(1) 907 # define DP_BSTATUS_READY BIT(0) 908 #define DP_AUX_HDCP_BINFO 0x6802A 909 #define DP_AUX_HDCP_KSV_FIFO 0x6802C 910 #define DP_AUX_HDCP_AINFO 0x6803B 911 912 /* DP 1.2 Sideband message defines */ 913 /* peer device type - DP 1.2a Table 2-92 */ 914 #define DP_PEER_DEVICE_NONE 0x0 915 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 916 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 917 #define DP_PEER_DEVICE_SST_SINK 0x3 918 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 919 920 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 921 #define DP_LINK_ADDRESS 0x01 922 #define DP_CONNECTION_STATUS_NOTIFY 0x02 923 #define DP_ENUM_PATH_RESOURCES 0x10 924 #define DP_ALLOCATE_PAYLOAD 0x11 925 #define DP_QUERY_PAYLOAD 0x12 926 #define DP_RESOURCE_STATUS_NOTIFY 0x13 927 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 928 #define DP_REMOTE_DPCD_READ 0x20 929 #define DP_REMOTE_DPCD_WRITE 0x21 930 #define DP_REMOTE_I2C_READ 0x22 931 #define DP_REMOTE_I2C_WRITE 0x23 932 #define DP_POWER_UP_PHY 0x24 933 #define DP_POWER_DOWN_PHY 0x25 934 #define DP_SINK_EVENT_NOTIFY 0x30 935 #define DP_QUERY_STREAM_ENC_STATUS 0x38 936 937 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 938 #define DP_NAK_WRITE_FAILURE 0x01 939 #define DP_NAK_INVALID_READ 0x02 940 #define DP_NAK_CRC_FAILURE 0x03 941 #define DP_NAK_BAD_PARAM 0x04 942 #define DP_NAK_DEFER 0x05 943 #define DP_NAK_LINK_FAILURE 0x06 944 #define DP_NAK_NO_RESOURCES 0x07 945 #define DP_NAK_DPCD_FAIL 0x08 946 #define DP_NAK_I2C_NAK 0x09 947 #define DP_NAK_ALLOCATE_FAIL 0x0a 948 949 #define MODE_I2C_START 1 950 #define MODE_I2C_WRITE 2 951 #define MODE_I2C_READ 4 952 #define MODE_I2C_STOP 8 953 954 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 955 #define DP_MST_PHYSICAL_PORT_0 0 956 #define DP_MST_LOGICAL_PORT_0 8 957 958 #define DP_LINK_STATUS_SIZE 6 959 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 960 int lane_count); 961 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 962 int lane_count); 963 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 964 int lane); 965 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 966 int lane); 967 968 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 969 #define DP_RECEIVER_CAP_SIZE 0xf 970 #define EDP_PSR_RECEIVER_CAP_SIZE 2 971 #define EDP_DISPLAY_CTL_CAP_SIZE 3 972 973 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 974 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 975 976 u8 drm_dp_link_rate_to_bw_code(int link_rate); 977 int drm_dp_bw_code_to_link_rate(u8 link_bw); 978 979 #define DP_SDP_AUDIO_TIMESTAMP 0x01 980 #define DP_SDP_AUDIO_STREAM 0x02 981 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ 982 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ 983 #define DP_SDP_ISRC 0x06 /* DP 1.2 */ 984 #define DP_SDP_VSC 0x07 /* DP 1.2 */ 985 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ 986 #define DP_SDP_PPS 0x10 /* DP 1.4 */ 987 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ 988 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ 989 /* 0x80+ CEA-861 infoframe types */ 990 991 struct dp_sdp_header { 992 u8 HB0; /* Secondary Data Packet ID */ 993 u8 HB1; /* Secondary Data Packet Type */ 994 u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */ 995 u8 HB3; /* Secondary Data packet Specific header, Byte 1 */ 996 } __packed; 997 998 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 999 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 1000 1001 struct edp_vsc_psr { 1002 struct dp_sdp_header sdp_header; 1003 u8 DB0; /* Stereo Interface */ 1004 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ 1005 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ 1006 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ 1007 u8 DB4; /* CRC value bits 7:0 of the G or Y component */ 1008 u8 DB5; /* CRC value bits 15:8 of the G or Y component */ 1009 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ 1010 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ 1011 u8 DB8_31[24]; /* Reserved */ 1012 } __packed; 1013 1014 #define EDP_VSC_PSR_STATE_ACTIVE (1 << 0) 1015 #define EDP_VSC_PSR_UPDATE_RFB (1 << 1) 1016 #define EDP_VSC_PSR_CRC_VALUES_VALID (1 << 2) 1017 1018 static inline int 1019 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1020 { 1021 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 1022 } 1023 1024 static inline u8 1025 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1026 { 1027 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 1028 } 1029 1030 static inline bool 1031 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1032 { 1033 return dpcd[DP_DPCD_REV] >= 0x11 && 1034 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 1035 } 1036 1037 static inline bool 1038 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1039 { 1040 return dpcd[DP_DPCD_REV] >= 0x12 && 1041 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 1042 } 1043 1044 static inline bool 1045 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1046 { 1047 return dpcd[DP_DPCD_REV] >= 0x14 && 1048 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 1049 } 1050 1051 static inline u8 1052 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1053 { 1054 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 1055 DP_TRAINING_PATTERN_MASK; 1056 } 1057 1058 static inline bool 1059 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1060 { 1061 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 1062 } 1063 1064 #endif /* _DRM_DP_HELPER_H_ */ 1065