1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright © 2008 Keith Packard 4 * 5 * Permission to use, copy, modify, distribute, and sell this software and its 6 * documentation for any purpose is hereby granted without fee, provided that 7 * the above copyright notice appear in all copies and that both that copyright 8 * notice and this permission notice appear in supporting documentation, and 9 * that the name of the copyright holders not be used in advertising or 10 * publicity pertaining to distribution of the software without specific, 11 * written prior permission. The copyright holders make no representations 12 * about the suitability of this software for any purpose. It is provided "as 13 * is" without express or implied warranty. 14 * 15 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 16 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 17 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 19 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 20 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 21 * OF THIS SOFTWARE. 22 */ 23 24 #ifndef _DRM_DP_HELPER_H_ 25 #define _DRM_DP_HELPER_H_ 26 27 #include <edid.h> 28 29 /* 30 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 31 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 32 * 1.0 devices basically don't exist in the wild. 33 * 34 * Abbreviations, in chronological order: 35 * 36 * eDP: Embedded DisplayPort version 1 37 * DPI: DisplayPort Interoperability Guideline v1.1a 38 * 1.2: DisplayPort 1.2 39 * MST: Multistream Transport - part of DP 1.2a 40 * 41 * 1.2 formally includes both eDP and DPI definitions. 42 */ 43 44 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ 45 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0) 46 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) 47 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9) 48 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) 49 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) 50 /* bits per component for non-RAW */ 51 #define DP_MSA_MISC_6_BPC (0 << 5) 52 #define DP_MSA_MISC_8_BPC (1 << 5) 53 #define DP_MSA_MISC_10_BPC (2 << 5) 54 #define DP_MSA_MISC_12_BPC (3 << 5) 55 #define DP_MSA_MISC_16_BPC (4 << 5) 56 /* bits per component for RAW */ 57 #define DP_MSA_MISC_RAW_6_BPC (1 << 5) 58 #define DP_MSA_MISC_RAW_7_BPC (2 << 5) 59 #define DP_MSA_MISC_RAW_8_BPC (3 << 5) 60 #define DP_MSA_MISC_RAW_10_BPC (4 << 5) 61 #define DP_MSA_MISC_RAW_12_BPC (5 << 5) 62 #define DP_MSA_MISC_RAW_14_BPC (6 << 5) 63 #define DP_MSA_MISC_RAW_16_BPC (7 << 5) 64 /* pixel encoding/colorimetry format */ 65 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ 66 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) 67 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) 68 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) 69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) 70 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) 71 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) 72 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) 73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) 74 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) 75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) 76 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) 77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) 78 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) 79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) 80 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) 81 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) 82 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) 83 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) 84 #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) 85 86 #define DP_AUX_MAX_PAYLOAD_BYTES 16 87 88 #define DP_AUX_I2C_WRITE 0x0 89 #define DP_AUX_I2C_READ 0x1 90 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 91 #define DP_AUX_I2C_MOT 0x4 92 #define DP_AUX_NATIVE_WRITE 0x8 93 #define DP_AUX_NATIVE_READ 0x9 94 95 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 96 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 97 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 98 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 99 100 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 101 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 102 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 103 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 104 105 /* AUX CH addresses */ 106 /* DPCD */ 107 #define DP_DPCD_REV 0x000 108 # define DP_DPCD_REV_10 0x10 109 # define DP_DPCD_REV_11 0x11 110 # define DP_DPCD_REV_12 0x12 111 # define DP_DPCD_REV_13 0x13 112 # define DP_DPCD_REV_14 0x14 113 114 #define DP_MAX_LINK_RATE 0x001 115 116 #define DP_MAX_LANE_COUNT 0x002 117 # define DP_MAX_LANE_COUNT_MASK 0x1f 118 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 119 # define DP_ENHANCED_FRAME_CAP (1 << 7) 120 121 #define DP_MAX_DOWNSPREAD 0x003 122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) 123 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 124 # define DP_TPS4_SUPPORTED (1 << 7) 125 126 #define DP_NORP 0x004 127 128 #define DP_DOWNSTREAMPORT_PRESENT 0x005 129 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 130 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 131 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 132 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 133 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 134 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 135 # define DP_FORMAT_CONVERSION (1 << 3) 136 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 137 138 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 139 # define DP_CAP_ANSI_8B10B (1 << 0) 140 141 #define DP_DOWN_STREAM_PORT_COUNT 0x007 142 # define DP_PORT_COUNT_MASK 0x0f 143 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 144 # define DP_OUI_SUPPORT (1 << 7) 145 146 #define DP_RECEIVE_PORT_0_CAP_0 0x008 147 # define DP_LOCAL_EDID_PRESENT (1 << 1) 148 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 149 150 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 151 152 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 153 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 154 155 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 156 # define DP_I2C_SPEED_1K 0x01 157 # define DP_I2C_SPEED_5K 0x02 158 # define DP_I2C_SPEED_10K 0x04 159 # define DP_I2C_SPEED_100K 0x08 160 # define DP_I2C_SPEED_400K 0x10 161 # define DP_I2C_SPEED_1M 0x20 162 163 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 164 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 165 # define DP_FRAMING_CHANGE_CAP (1 << 1) 166 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 167 168 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 169 # define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */ 170 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ 171 172 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 173 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 174 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 175 176 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 177 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 178 179 /* Multiple stream transport */ 180 #define DP_FAUX_CAP 0x020 /* 1.2 */ 181 # define DP_FAUX_CAP_1 (1 << 0) 182 183 #define DP_MSTM_CAP 0x021 /* 1.2 */ 184 # define DP_MST_CAP (1 << 0) 185 186 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 187 188 /* AV_SYNC_DATA_BLOCK 1.2 */ 189 #define DP_AV_GRANULARITY 0x023 190 # define DP_AG_FACTOR_MASK (0xf << 0) 191 # define DP_AG_FACTOR_3MS (0 << 0) 192 # define DP_AG_FACTOR_2MS (1 << 0) 193 # define DP_AG_FACTOR_1MS (2 << 0) 194 # define DP_AG_FACTOR_500US (3 << 0) 195 # define DP_AG_FACTOR_200US (4 << 0) 196 # define DP_AG_FACTOR_100US (5 << 0) 197 # define DP_AG_FACTOR_10US (6 << 0) 198 # define DP_AG_FACTOR_1US (7 << 0) 199 # define DP_VG_FACTOR_MASK (0xf << 4) 200 # define DP_VG_FACTOR_3MS (0 << 4) 201 # define DP_VG_FACTOR_2MS (1 << 4) 202 # define DP_VG_FACTOR_1MS (2 << 4) 203 # define DP_VG_FACTOR_500US (3 << 4) 204 # define DP_VG_FACTOR_200US (4 << 4) 205 # define DP_VG_FACTOR_100US (5 << 4) 206 207 #define DP_AUD_DEC_LAT0 0x024 208 #define DP_AUD_DEC_LAT1 0x025 209 210 #define DP_AUD_PP_LAT0 0x026 211 #define DP_AUD_PP_LAT1 0x027 212 213 #define DP_VID_INTER_LAT 0x028 214 215 #define DP_VID_PROG_LAT 0x029 216 217 #define DP_REP_LAT 0x02a 218 219 #define DP_AUD_DEL_INS0 0x02b 220 #define DP_AUD_DEL_INS1 0x02c 221 #define DP_AUD_DEL_INS2 0x02d 222 /* End of AV_SYNC_DATA_BLOCK */ 223 224 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 225 # define DP_ALPM_CAP (1 << 0) 226 227 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 228 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 229 230 #define DP_GUID 0x030 /* 1.2 */ 231 232 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ 233 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) 234 235 #define DP_DSC_REV 0x061 236 # define DP_DSC_MAJOR_MASK (0xf << 0) 237 # define DP_DSC_MINOR_MASK (0xf << 4) 238 # define DP_DSC_MAJOR_SHIFT 0 239 # define DP_DSC_MINOR_SHIFT 4 240 241 #define DP_DSC_RC_BUF_BLK_SIZE 0x062 242 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 243 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 244 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 245 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 246 247 #define DP_DSC_RC_BUF_SIZE 0x063 248 249 #define DP_DSC_SLICE_CAP_1 0x064 250 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) 251 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) 252 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) 253 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) 254 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) 255 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) 256 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) 257 258 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 259 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) 260 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 261 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 262 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 263 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 264 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 265 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 266 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 267 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 268 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 269 270 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 271 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) 272 273 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ 274 275 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ 276 277 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 278 # define DP_DSC_RGB (1 << 0) 279 # define DP_DSC_YCbCr444 (1 << 1) 280 # define DP_DSC_YCbCr422_Simple (1 << 2) 281 # define DP_DSC_YCbCr422_Native (1 << 3) 282 # define DP_DSC_YCbCr420_Native (1 << 4) 283 284 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A 285 # define DP_DSC_8_BPC (1 << 1) 286 # define DP_DSC_10_BPC (1 << 2) 287 # define DP_DSC_12_BPC (1 << 3) 288 289 #define DP_DSC_PEAK_THROUGHPUT 0x06B 290 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) 291 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 292 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) 293 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) 294 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) 295 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) 296 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) 297 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) 298 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) 299 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) 300 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) 301 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) 302 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) 303 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) 304 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) 305 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) 306 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) 307 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 308 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) 309 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) 310 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) 311 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) 312 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) 313 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) 314 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) 315 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) 316 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) 317 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) 318 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) 319 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) 320 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) 321 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) 322 323 #define DP_DSC_MAX_SLICE_WIDTH 0x06C 324 325 #define DP_DSC_SLICE_CAP_2 0x06D 326 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) 327 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) 328 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) 329 330 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F 331 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 332 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 333 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 334 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 335 # define DP_DSC_BITS_PER_PIXEL_1 0x4 336 337 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 338 # define DP_PSR_IS_SUPPORTED 1 339 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 340 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ 341 342 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 343 # define DP_PSR_NO_TRAIN_ON_EXIT 1 344 # define DP_PSR_SETUP_TIME_330 (0 << 1) 345 # define DP_PSR_SETUP_TIME_275 (1 << 1) 346 # define DP_PSR_SETUP_TIME_220 (2 << 1) 347 # define DP_PSR_SETUP_TIME_165 (3 << 1) 348 # define DP_PSR_SETUP_TIME_110 (4 << 1) 349 # define DP_PSR_SETUP_TIME_55 (5 << 1) 350 # define DP_PSR_SETUP_TIME_0 (6 << 1) 351 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 352 # define DP_PSR_SETUP_TIME_SHIFT 1 353 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ 354 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ 355 /* 356 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 357 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 358 * each port's descriptor is one byte wide. If it was set, each port's is 359 * four bytes wide, starting with the one byte from the base info. As of 360 * DP interop v1.1a only VGA defines additional detail. 361 */ 362 363 /* offset 0 */ 364 #define DP_DOWNSTREAM_PORT_0 0x80 365 # define DP_DS_PORT_TYPE_MASK (7 << 0) 366 # define DP_DS_PORT_TYPE_DP 0 367 # define DP_DS_PORT_TYPE_VGA 1 368 # define DP_DS_PORT_TYPE_DVI 2 369 # define DP_DS_PORT_TYPE_HDMI 3 370 # define DP_DS_PORT_TYPE_NON_EDID 4 371 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 372 # define DP_DS_PORT_TYPE_WIRELESS 6 373 # define DP_DS_PORT_HPD (1 << 3) 374 /* offset 1 for VGA is maximum megapixels per second / 8 */ 375 /* offset 2 */ 376 # define DP_DS_MAX_BPC_MASK (3 << 0) 377 # define DP_DS_8BPC 0 378 # define DP_DS_10BPC 1 379 # define DP_DS_12BPC 2 380 # define DP_DS_16BPC 3 381 382 /* DP Forward error Correction Registers */ 383 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */ 384 # define DP_FEC_CAPABLE (1 << 0) 385 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) 386 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) 387 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) 388 389 /* link configuration */ 390 #define DP_LINK_BW_SET 0x100 391 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 392 # define DP_LINK_BW_1_62 0x06 393 # define DP_LINK_BW_2_7 0x0a 394 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 395 # define DP_LINK_BW_8_1 0x1e /* 1.4 */ 396 397 #define DP_LANE_COUNT_SET 0x101 398 # define DP_LANE_COUNT_MASK 0x0f 399 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 400 401 #define DP_TRAINING_PATTERN_SET 0x102 402 # define DP_TRAINING_PATTERN_DISABLE 0 403 # define DP_TRAINING_PATTERN_1 1 404 # define DP_TRAINING_PATTERN_2 2 405 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 406 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */ 407 # define DP_TRAINING_PATTERN_MASK 0x3 408 # define DP_TRAINING_PATTERN_MASK_1_4 0xf 409 410 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 411 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 412 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 413 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 414 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 415 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 416 417 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 418 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 419 420 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 421 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 422 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 423 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 424 425 #define DP_TRAINING_LANE0_SET 0x103 426 #define DP_TRAINING_LANE1_SET 0x104 427 #define DP_TRAINING_LANE2_SET 0x105 428 #define DP_TRAINING_LANE3_SET 0x106 429 430 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 431 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 432 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 433 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 434 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 435 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 436 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 437 438 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 439 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 440 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 441 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 442 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 443 444 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 445 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 446 447 #define DP_DOWNSPREAD_CTRL 0x107 448 # define DP_SPREAD_AMP_0_5 (1 << 4) 449 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 450 451 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 452 # define DP_SET_ANSI_8B10B (1 << 0) 453 454 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 455 /* bitmask as for DP_I2C_SPEED_CAP */ 456 457 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 458 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 459 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 460 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 461 462 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 463 #define DP_LINK_QUAL_LANE1_SET 0x10c 464 #define DP_LINK_QUAL_LANE2_SET 0x10d 465 #define DP_LINK_QUAL_LANE3_SET 0x10e 466 # define DP_LINK_QUAL_PATTERN_DISABLE 0 467 # define DP_LINK_QUAL_PATTERN_D10_2 1 468 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 469 # define DP_LINK_QUAL_PATTERN_PRBS7 3 470 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 471 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 472 # define DP_LINK_QUAL_PATTERN_MASK 7 473 474 #define DP_TRAINING_LANE0_1_SET2 0x10f 475 #define DP_TRAINING_LANE2_3_SET2 0x110 476 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 477 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 478 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 479 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 480 481 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 482 # define DP_MST_EN (1 << 0) 483 # define DP_UP_REQ_EN (1 << 1) 484 # define DP_UPSTREAM_IS_SRC (1 << 2) 485 486 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 487 #define DP_AUDIO_DELAY1 0x113 488 #define DP_AUDIO_DELAY2 0x114 489 490 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 491 # define DP_LINK_RATE_SET_SHIFT 0 492 # define DP_LINK_RATE_SET_MASK (7 << 0) 493 494 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 495 # define DP_ALPM_ENABLE (1 << 0) 496 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 497 498 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 499 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 500 # define DP_IRQ_HPD_ENABLE (1 << 1) 501 502 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 503 # define DP_PWR_NOT_NEEDED (1 << 0) 504 505 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ 506 # define DP_FEC_READY (1 << 0) 507 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) 508 # define DP_FEC_ERR_COUNT_DIS (0 << 1) 509 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) 510 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) 511 # define DP_FEC_BIT_ERROR_COUNT (3 << 1) 512 # define DP_FEC_LANE_SELECT_MASK (3 << 4) 513 # define DP_FEC_LANE_0_SELECT (0 << 4) 514 # define DP_FEC_LANE_1_SELECT (1 << 4) 515 # define DP_FEC_LANE_2_SELECT (2 << 4) 516 # define DP_FEC_LANE_3_SELECT (3 << 4) 517 518 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 519 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 520 521 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ 522 523 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 524 # define DP_PSR_ENABLE (1 << 0) 525 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 526 # define DP_PSR_CRC_VERIFICATION (1 << 2) 527 # define DP_PSR_FRAME_CAPTURE (1 << 3) 528 # define DP_PSR_SELECTIVE_UPDATE (1 << 4) 529 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) 530 # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ 531 532 #define DP_ADAPTER_CTRL 0x1a0 533 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 534 535 #define DP_BRANCH_DEVICE_CTRL 0x1a1 536 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 537 538 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 539 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 540 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 541 542 #define DP_SINK_COUNT 0x200 543 /* prior to 1.2 bit 7 was reserved mbz */ 544 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 545 # define DP_SINK_CP_READY (1 << 6) 546 547 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 548 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 549 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 550 # define DP_CP_IRQ (1 << 2) 551 # define DP_MCCS_IRQ (1 << 3) 552 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 553 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 554 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 555 556 #define DP_LANE0_1_STATUS 0x202 557 #define DP_LANE2_3_STATUS 0x203 558 # define DP_LANE_CR_DONE (1 << 0) 559 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 560 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 561 562 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 563 DP_LANE_CHANNEL_EQ_DONE | \ 564 DP_LANE_SYMBOL_LOCKED) 565 566 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 567 568 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 569 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 570 #define DP_LINK_STATUS_UPDATED (1 << 7) 571 572 #define DP_SINK_STATUS 0x205 573 574 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 575 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 576 577 #define DP_ADJUST_REQUEST_LANE0_1 0x206 578 #define DP_ADJUST_REQUEST_LANE2_3 0x207 579 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 580 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 581 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 582 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 583 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 584 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 585 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 586 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 587 588 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c 589 590 #define DP_TEST_REQUEST 0x218 591 # define DP_TEST_LINK_TRAINING (1 << 0) 592 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 593 # define DP_TEST_LINK_EDID_READ (1 << 2) 594 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 595 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 596 597 #define DP_TEST_LINK_RATE 0x219 598 # define DP_LINK_RATE_162 (0x6) 599 # define DP_LINK_RATE_27 (0xa) 600 601 #define DP_TEST_LANE_COUNT 0x220 602 603 #define DP_TEST_PATTERN 0x221 604 # define DP_NO_TEST_PATTERN 0x0 605 # define DP_COLOR_RAMP 0x1 606 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 607 # define DP_COLOR_SQUARE 0x3 608 609 #define DP_TEST_H_TOTAL_HI 0x222 610 #define DP_TEST_H_TOTAL_LO 0x223 611 612 #define DP_TEST_V_TOTAL_HI 0x224 613 #define DP_TEST_V_TOTAL_LO 0x225 614 615 #define DP_TEST_H_START_HI 0x226 616 #define DP_TEST_H_START_LO 0x227 617 618 #define DP_TEST_V_START_HI 0x228 619 #define DP_TEST_V_START_LO 0x229 620 621 #define DP_TEST_HSYNC_HI 0x22A 622 # define DP_TEST_HSYNC_POLARITY (1 << 7) 623 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) 624 #define DP_TEST_HSYNC_WIDTH_LO 0x22B 625 626 #define DP_TEST_VSYNC_HI 0x22C 627 # define DP_TEST_VSYNC_POLARITY (1 << 7) 628 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) 629 #define DP_TEST_VSYNC_WIDTH_LO 0x22D 630 631 #define DP_TEST_H_WIDTH_HI 0x22E 632 #define DP_TEST_H_WIDTH_LO 0x22F 633 634 #define DP_TEST_V_HEIGHT_HI 0x230 635 #define DP_TEST_V_HEIGHT_LO 0x231 636 637 #define DP_TEST_MISC0 0x232 638 # define DP_TEST_SYNC_CLOCK (1 << 0) 639 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) 640 # define DP_TEST_COLOR_FORMAT_SHIFT 1 641 # define DP_COLOR_FORMAT_RGB (0 << 1) 642 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) 643 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) 644 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) 645 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) 646 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) 647 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) 648 # define DP_TEST_BIT_DEPTH_MASK (7 << 5) 649 # define DP_TEST_BIT_DEPTH_SHIFT 5 650 # define DP_TEST_BIT_DEPTH_6 (0 << 5) 651 # define DP_TEST_BIT_DEPTH_8 (1 << 5) 652 # define DP_TEST_BIT_DEPTH_10 (2 << 5) 653 # define DP_TEST_BIT_DEPTH_12 (3 << 5) 654 # define DP_TEST_BIT_DEPTH_16 (4 << 5) 655 656 #define DP_TEST_MISC1 0x233 657 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) 658 # define DP_TEST_INTERLACED (1 << 1) 659 660 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 661 662 #define DP_TEST_MISC0 0x232 663 664 #define DP_TEST_CRC_R_CR 0x240 665 #define DP_TEST_CRC_G_Y 0x242 666 #define DP_TEST_CRC_B_CB 0x244 667 668 #define DP_TEST_SINK_MISC 0x246 669 # define DP_TEST_CRC_SUPPORTED (1 << 5) 670 # define DP_TEST_COUNT_MASK 0xf 671 672 #define DP_TEST_PHY_PATTERN 0x248 673 # define DP_TEST_PHY_PATTERN_NONE 0x0 674 # define DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING 0x1 675 # define DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT 0x2 676 # define DP_TEST_PHY_PATTERN_PRBS7 0x3 677 # define DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN 0x4 678 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_1 0x5 679 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_2 0x6 680 # define DP_TEST_PHY_PATTERN_CP2520_PATTERN_3 0x7 681 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 682 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 683 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 684 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 685 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 686 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 687 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 688 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 689 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 690 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 691 692 #define DP_TEST_RESPONSE 0x260 693 # define DP_TEST_ACK (1 << 0) 694 # define DP_TEST_NAK (1 << 1) 695 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 696 697 #define DP_TEST_EDID_CHECKSUM 0x261 698 699 #define DP_TEST_SINK 0x270 700 # define DP_TEST_SINK_START (1 << 0) 701 702 #define DP_FEC_STATUS 0x280 /* 1.4 */ 703 # define DP_FEC_DECODE_EN_DETECTED (1 << 0) 704 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1) 705 706 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ 707 708 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ 709 # define DP_FEC_ERROR_COUNT_MASK 0x7F 710 # define DP_FEC_ERR_COUNT_VALID (1 << 7) 711 712 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 713 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 714 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 715 716 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 717 /* up to ID_SLOT_63 at 0x2ff */ 718 719 #define DP_SOURCE_OUI 0x300 720 #define DP_SINK_OUI 0x400 721 #define DP_BRANCH_OUI 0x500 722 #define DP_BRANCH_ID 0x503 723 #define DP_BRANCH_REVISION_START 0x509 724 #define DP_BRANCH_HW_REV 0x509 725 #define DP_BRANCH_SW_REV 0x50A 726 727 #define DP_SET_POWER 0x600 728 # define DP_SET_POWER_D0 0x1 729 # define DP_SET_POWER_D3 0x2 730 # define DP_SET_POWER_MASK 0x3 731 # define DP_SET_POWER_D3_AUX_ON 0x5 732 733 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 734 # define DP_EDP_11 0x00 735 # define DP_EDP_12 0x01 736 # define DP_EDP_13 0x02 737 # define DP_EDP_14 0x03 738 739 #define DP_EDP_GENERAL_CAP_1 0x701 740 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 741 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 742 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 743 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 744 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 745 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 746 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 747 # define DP_EDP_SET_POWER_CAP (1 << 7) 748 749 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 750 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 751 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 752 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 753 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 754 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 755 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 756 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 757 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 758 759 #define DP_EDP_GENERAL_CAP_2 0x703 760 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 761 762 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 763 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 764 # define DP_EDP_X_REGION_CAP_SHIFT 0 765 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 766 # define DP_EDP_Y_REGION_CAP_SHIFT 4 767 768 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 769 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 770 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 771 # define DP_EDP_FRC_ENABLE (1 << 2) 772 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 773 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 774 775 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 776 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 777 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 778 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 779 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 780 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 781 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 782 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 783 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 784 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 785 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 786 787 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 788 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 789 790 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 791 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 792 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 793 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) 794 795 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 796 797 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 798 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 799 800 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 801 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 802 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 803 804 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 805 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 806 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 807 808 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 809 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 810 811 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 812 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 813 814 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 815 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 816 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 817 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 818 819 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 820 /* 0-5 sink count */ 821 # define DP_SINK_COUNT_CP_READY (1 << 6) 822 823 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 824 825 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 826 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) 827 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1) 828 # define DP_CEC_IRQ (1 << 2) 829 830 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 831 832 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 833 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 834 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 835 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 836 837 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 838 # define DP_PSR_CAPS_CHANGE (1 << 0) 839 840 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 841 # define DP_PSR_SINK_INACTIVE 0 842 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 843 # define DP_PSR_SINK_ACTIVE_RFB 2 844 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 845 # define DP_PSR_SINK_ACTIVE_RESYNC 4 846 # define DP_PSR_SINK_INTERNAL_ERROR 7 847 # define DP_PSR_SINK_STATE_MASK 0x07 848 849 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ 850 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) 851 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 852 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) 853 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 854 855 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ 856 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ 857 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ 858 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ 859 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */ 860 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ 861 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ 862 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ 863 864 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 865 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 866 867 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ 868 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ 869 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ 870 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ 871 872 #define DP_DP13_DPCD_REV 0x2200 873 #define DP_DP13_MAX_LINK_RATE 0x2201 874 875 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ 876 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ 877 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ 878 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ 879 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ 880 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ 881 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ 882 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ 883 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ 884 885 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ 886 #define DP_CEC_TUNNELING_CAPABILITY 0x3000 887 # define DP_CEC_TUNNELING_CAPABLE (1 << 0) 888 # define DP_CEC_SNOOPING_CAPABLE (1 << 1) 889 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) 890 891 #define DP_CEC_TUNNELING_CONTROL 0x3001 892 # define DP_CEC_TUNNELING_ENABLE (1 << 0) 893 # define DP_CEC_SNOOPING_ENABLE (1 << 1) 894 895 #define DP_CEC_RX_MESSAGE_INFO 0x3002 896 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) 897 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 898 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) 899 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) 900 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6) 901 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7) 902 903 #define DP_CEC_TX_MESSAGE_INFO 0x3003 904 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) 905 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 906 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) 907 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4 908 # define DP_CEC_TX_MESSAGE_SEND (1 << 7) 909 910 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 911 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) 912 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) 913 # define DP_CEC_TX_MESSAGE_SENT (1 << 4) 914 # define DP_CEC_TX_LINE_ERROR (1 << 5) 915 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) 916 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) 917 918 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ 919 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) 920 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) 921 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) 922 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) 923 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) 924 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) 925 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) 926 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) 927 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ 928 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) 929 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) 930 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) 931 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) 932 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) 933 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) 934 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) 935 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) 936 937 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010 938 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 939 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 940 941 #define DP_AUX_HDCP_BKSV 0x68000 942 #define DP_AUX_HDCP_RI_PRIME 0x68005 943 #define DP_AUX_HDCP_AKSV 0x68007 944 #define DP_AUX_HDCP_AN 0x6800C 945 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + (h) * 4) 946 #define DP_AUX_HDCP_BCAPS 0x68028 947 # define DP_BCAPS_REPEATER_PRESENT BIT(1) 948 # define DP_BCAPS_HDCP_CAPABLE BIT(0) 949 #define DP_AUX_HDCP_BSTATUS 0x68029 950 # define DP_BSTATUS_REAUTH_REQ BIT(3) 951 # define DP_BSTATUS_LINK_FAILURE BIT(2) 952 # define DP_BSTATUS_R0_PRIME_READY BIT(1) 953 # define DP_BSTATUS_READY BIT(0) 954 #define DP_AUX_HDCP_BINFO 0x6802A 955 #define DP_AUX_HDCP_KSV_FIFO 0x6802C 956 #define DP_AUX_HDCP_AINFO 0x6803B 957 958 /* DP 1.2 Sideband message defines */ 959 /* peer device type - DP 1.2a Table 2-92 */ 960 #define DP_PEER_DEVICE_NONE 0x0 961 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 962 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 963 #define DP_PEER_DEVICE_SST_SINK 0x3 964 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 965 966 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 967 #define DP_LINK_ADDRESS 0x01 968 #define DP_CONNECTION_STATUS_NOTIFY 0x02 969 #define DP_ENUM_PATH_RESOURCES 0x10 970 #define DP_ALLOCATE_PAYLOAD 0x11 971 #define DP_QUERY_PAYLOAD 0x12 972 #define DP_RESOURCE_STATUS_NOTIFY 0x13 973 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 974 #define DP_REMOTE_DPCD_READ 0x20 975 #define DP_REMOTE_DPCD_WRITE 0x21 976 #define DP_REMOTE_I2C_READ 0x22 977 #define DP_REMOTE_I2C_WRITE 0x23 978 #define DP_POWER_UP_PHY 0x24 979 #define DP_POWER_DOWN_PHY 0x25 980 #define DP_SINK_EVENT_NOTIFY 0x30 981 #define DP_QUERY_STREAM_ENC_STATUS 0x38 982 983 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 984 #define DP_NAK_WRITE_FAILURE 0x01 985 #define DP_NAK_INVALID_READ 0x02 986 #define DP_NAK_CRC_FAILURE 0x03 987 #define DP_NAK_BAD_PARAM 0x04 988 #define DP_NAK_DEFER 0x05 989 #define DP_NAK_LINK_FAILURE 0x06 990 #define DP_NAK_NO_RESOURCES 0x07 991 #define DP_NAK_DPCD_FAIL 0x08 992 #define DP_NAK_I2C_NAK 0x09 993 #define DP_NAK_ALLOCATE_FAIL 0x0a 994 995 #define MODE_I2C_START 1 996 #define MODE_I2C_WRITE 2 997 #define MODE_I2C_READ 4 998 #define MODE_I2C_STOP 8 999 1000 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 1001 #define DP_MST_PHYSICAL_PORT_0 0 1002 #define DP_MST_LOGICAL_PORT_0 8 1003 1004 #define DP_LINK_STATUS_SIZE 6 1005 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 1006 int lane_count); 1007 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 1008 int lane_count); 1009 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 1010 int lane); 1011 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 1012 int lane); 1013 1014 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 1015 #define DP_RECEIVER_CAP_SIZE 0xf 1016 #define EDP_PSR_RECEIVER_CAP_SIZE 2 1017 #define EDP_DISPLAY_CTL_CAP_SIZE 3 1018 1019 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 1020 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 1021 1022 u8 drm_dp_link_rate_to_bw_code(int link_rate); 1023 int drm_dp_bw_code_to_link_rate(u8 link_bw); 1024 1025 #define DP_SDP_AUDIO_TIMESTAMP 0x01 1026 #define DP_SDP_AUDIO_STREAM 0x02 1027 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ 1028 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ 1029 #define DP_SDP_ISRC 0x06 /* DP 1.2 */ 1030 #define DP_SDP_VSC 0x07 /* DP 1.2 */ 1031 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ 1032 #define DP_SDP_PPS 0x10 /* DP 1.4 */ 1033 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ 1034 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ 1035 /* 0x80+ CEA-861 infoframe types */ 1036 1037 struct dp_sdp_header { 1038 u8 HB0; /* Secondary Data Packet ID */ 1039 u8 HB1; /* Secondary Data Packet Type */ 1040 u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */ 1041 u8 HB3; /* Secondary Data packet Specific header, Byte 1 */ 1042 } __packed; 1043 1044 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 1045 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 1046 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F 1047 1048 struct edp_vsc_psr { 1049 struct dp_sdp_header sdp_header; 1050 u8 DB0; /* Stereo Interface */ 1051 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ 1052 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ 1053 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ 1054 u8 DB4; /* CRC value bits 7:0 of the G or Y component */ 1055 u8 DB5; /* CRC value bits 15:8 of the G or Y component */ 1056 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ 1057 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ 1058 u8 DB8_31[24]; /* Reserved */ 1059 } __packed; 1060 1061 #define EDP_VSC_PSR_STATE_ACTIVE (1 << 0) 1062 #define EDP_VSC_PSR_UPDATE_RFB (1 << 1) 1063 #define EDP_VSC_PSR_CRC_VALUES_VALID (1 << 2) 1064 1065 enum dp_pixelformat { 1066 DP_PIXELFORMAT_RGB = 0, 1067 DP_PIXELFORMAT_YUV444 = 0x1, 1068 DP_PIXELFORMAT_YUV422 = 0x2, 1069 DP_PIXELFORMAT_YUV420 = 0x3, 1070 DP_PIXELFORMAT_Y_ONLY = 0x4, 1071 DP_PIXELFORMAT_RAW = 0x5, 1072 DP_PIXELFORMAT_RESERVED = 0x6, 1073 }; 1074 1075 enum dp_colorimetry { 1076 DP_COLORIMETRY_DEFAULT = 0, 1077 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, 1078 DP_COLORIMETRY_BT709_YCC = 0x1, 1079 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, 1080 DP_COLORIMETRY_XVYCC_601 = 0x2, 1081 DP_COLORIMETRY_OPRGB = 0x3, 1082 DP_COLORIMETRY_XVYCC_709 = 0x3, 1083 DP_COLORIMETRY_DCI_P3_RGB = 0x4, 1084 DP_COLORIMETRY_SYCC_601 = 0x4, 1085 DP_COLORIMETRY_RGB_CUSTOM = 0x5, 1086 DP_COLORIMETRY_OPYCC_601 = 0x5, 1087 DP_COLORIMETRY_BT2020_RGB = 0x6, 1088 DP_COLORIMETRY_BT2020_CYCC = 0x6, 1089 DP_COLORIMETRY_BT2020_YCC = 0x7, 1090 }; 1091 1092 enum dp_dynamic_range { 1093 DP_DYNAMIC_RANGE_VESA = 0, 1094 DP_DYNAMIC_RANGE_CTA = 1, 1095 }; 1096 1097 enum dp_content_type { 1098 DP_CONTENT_TYPE_NOT_DEFINED = 0x00, 1099 DP_CONTENT_TYPE_GRAPHICS = 0x01, 1100 DP_CONTENT_TYPE_PHOTO = 0x02, 1101 DP_CONTENT_TYPE_VIDEO = 0x03, 1102 DP_CONTENT_TYPE_GAME = 0x04, 1103 }; 1104 1105 struct drm_dp_vsc_sdp { 1106 unsigned char sdp_type; 1107 unsigned char revision; 1108 unsigned char length; 1109 enum dp_pixelformat pixelformat; 1110 enum dp_colorimetry colorimetry; 1111 int bpc; 1112 enum dp_dynamic_range dynamic_range; 1113 enum dp_content_type content_type; 1114 }; 1115 1116 static inline int 1117 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1118 { 1119 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 1120 } 1121 1122 static inline u8 1123 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1124 { 1125 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 1126 } 1127 1128 static inline bool 1129 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1130 { 1131 return dpcd[DP_DPCD_REV] >= 0x11 && 1132 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 1133 } 1134 1135 static inline bool 1136 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1137 { 1138 return dpcd[DP_DPCD_REV] >= 0x12 && 1139 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 1140 } 1141 1142 static inline bool 1143 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1144 { 1145 return dpcd[DP_DPCD_REV] >= 0x14 && 1146 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 1147 } 1148 1149 static inline u8 1150 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1151 { 1152 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 1153 DP_TRAINING_PATTERN_MASK; 1154 } 1155 1156 static inline bool 1157 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1158 { 1159 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 1160 } 1161 1162 static inline bool 1163 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1164 { 1165 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 1166 } 1167 1168 static inline bool 1169 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1170 { 1171 return dpcd[DP_EDP_CONFIGURATION_CAP] & 1172 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 1173 } 1174 1175 struct drm_dp_aux_msg { 1176 unsigned int address; 1177 u8 request; 1178 u8 reply; 1179 void *buffer; 1180 size_t size; 1181 }; 1182 1183 struct drm_dp_aux { 1184 const char *name; 1185 struct ddc_adapter ddc; 1186 struct udevice *dev; 1187 ssize_t (*transfer)(struct drm_dp_aux *aux, 1188 struct drm_dp_aux_msg *msg); 1189 unsigned int i2c_nack_count; 1190 unsigned int i2c_defer_count; 1191 }; 1192 1193 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 1194 void *buffer, size_t size); 1195 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 1196 void *buffer, size_t size); 1197 1198 /** 1199 * drm_dp_dpcd_readb() - read a single byte from the DPCD 1200 * @aux: DisplayPort AUX channel 1201 * @offset: address of the register to read 1202 * @valuep: location where the value of the register will be stored 1203 * 1204 * Returns the number of bytes transferred (1) on success, or a negative 1205 * error code on failure. 1206 */ 1207 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 1208 unsigned int offset, u8 *valuep) 1209 { 1210 return drm_dp_dpcd_read(aux, offset, valuep, 1); 1211 } 1212 1213 /** 1214 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 1215 * @aux: DisplayPort AUX channel 1216 * @offset: address of the register to write 1217 * @value: value to write to the register 1218 * 1219 * Returns the number of bytes transferred (1) on success, or a negative 1220 * error code on failure. 1221 */ 1222 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 1223 unsigned int offset, u8 value) 1224 { 1225 return drm_dp_dpcd_write(aux, offset, &value, 1); 1226 } 1227 1228 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 1229 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 1230 1231 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 1232 u8 status[DP_LINK_STATUS_SIZE]); 1233 1234 int drm_dp_i2c_xfer(struct ddc_adapter *adapter, struct i2c_msg *msgs, 1235 int num); 1236 #endif /* _DRM_DP_HELPER_H_ */ 1237