1*59088e4aSNobuhiro Iwamatsu /* 2*59088e4aSNobuhiro Iwamatsu * Copyright (c) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3*59088e4aSNobuhiro Iwamatsu * Copyright (c) 2014 Renesas Electronics Corporation 4*59088e4aSNobuhiro Iwamatsu * 5*59088e4aSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 6*59088e4aSNobuhiro Iwamatsu */ 7*59088e4aSNobuhiro Iwamatsu 8*59088e4aSNobuhiro Iwamatsu #ifndef __serial_sh_h 9*59088e4aSNobuhiro Iwamatsu #define __serial_sh_h 10*59088e4aSNobuhiro Iwamatsu 11*59088e4aSNobuhiro Iwamatsu enum sh_clk_mode { 12*59088e4aSNobuhiro Iwamatsu INT_CLK, 13*59088e4aSNobuhiro Iwamatsu EXT_CLK, 14*59088e4aSNobuhiro Iwamatsu }; 15*59088e4aSNobuhiro Iwamatsu 16*59088e4aSNobuhiro Iwamatsu enum sh_serial_type { 17*59088e4aSNobuhiro Iwamatsu PORT_SCI, 18*59088e4aSNobuhiro Iwamatsu PORT_SCIF, 19*59088e4aSNobuhiro Iwamatsu PORT_SCIFA, 20*59088e4aSNobuhiro Iwamatsu PORT_SCIFB, 21*59088e4aSNobuhiro Iwamatsu }; 22*59088e4aSNobuhiro Iwamatsu 23*59088e4aSNobuhiro Iwamatsu /* 24*59088e4aSNobuhiro Iwamatsu * Information about SCIF port 25*59088e4aSNobuhiro Iwamatsu * 26*59088e4aSNobuhiro Iwamatsu * @base: Register base address 27*59088e4aSNobuhiro Iwamatsu * @clk: Input clock rate, used for calculating the baud rate divisor 28*59088e4aSNobuhiro Iwamatsu * @clk_mode: Clock mode, set internal (INT) or external (EXT) 29*59088e4aSNobuhiro Iwamatsu * @type: Type of SCIF 30*59088e4aSNobuhiro Iwamatsu */ 31*59088e4aSNobuhiro Iwamatsu struct sh_serial_platdata { 32*59088e4aSNobuhiro Iwamatsu unsigned long base; 33*59088e4aSNobuhiro Iwamatsu unsigned int clk; 34*59088e4aSNobuhiro Iwamatsu enum sh_clk_mode clk_mode; 35*59088e4aSNobuhiro Iwamatsu enum sh_serial_type type; 36*59088e4aSNobuhiro Iwamatsu }; 37*59088e4aSNobuhiro Iwamatsu #endif /* __serial_sh_h */ 38