1*cbfa67a1SMarcel Ziswiler /* 2*cbfa67a1SMarcel Ziswiler * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> 3*cbfa67a1SMarcel Ziswiler * 4*cbfa67a1SMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5*cbfa67a1SMarcel Ziswiler */ 6*cbfa67a1SMarcel Ziswiler 7*cbfa67a1SMarcel Ziswiler #ifndef __SERIAL_PXA_H 8*cbfa67a1SMarcel Ziswiler #define __SERIAL_PXA_H 9*cbfa67a1SMarcel Ziswiler 10*cbfa67a1SMarcel Ziswiler /* 11*cbfa67a1SMarcel Ziswiler * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can 12*cbfa67a1SMarcel Ziswiler * easily handle enabling of clock. 13*cbfa67a1SMarcel Ziswiler */ 14*cbfa67a1SMarcel Ziswiler #ifdef CONFIG_CPU_MONAHANS 15*cbfa67a1SMarcel Ziswiler #define UART_CLK_BASE CKENA_21_BTUART 16*cbfa67a1SMarcel Ziswiler #define UART_CLK_REG CKENA 17*cbfa67a1SMarcel Ziswiler #define BTUART_INDEX 0 18*cbfa67a1SMarcel Ziswiler #define FFUART_INDEX 1 19*cbfa67a1SMarcel Ziswiler #define STUART_INDEX 2 20*cbfa67a1SMarcel Ziswiler #elif CONFIG_CPU_PXA25X 21*cbfa67a1SMarcel Ziswiler #define UART_CLK_BASE (1 << 4) /* HWUART */ 22*cbfa67a1SMarcel Ziswiler #define UART_CLK_REG CKEN 23*cbfa67a1SMarcel Ziswiler #define HWUART_INDEX 0 24*cbfa67a1SMarcel Ziswiler #define STUART_INDEX 1 25*cbfa67a1SMarcel Ziswiler #define FFUART_INDEX 2 26*cbfa67a1SMarcel Ziswiler #define BTUART_INDEX 3 27*cbfa67a1SMarcel Ziswiler #else /* PXA27x */ 28*cbfa67a1SMarcel Ziswiler #define UART_CLK_BASE CKEN5_STUART 29*cbfa67a1SMarcel Ziswiler #define UART_CLK_REG CKEN 30*cbfa67a1SMarcel Ziswiler #define STUART_INDEX 0 31*cbfa67a1SMarcel Ziswiler #define FFUART_INDEX 1 32*cbfa67a1SMarcel Ziswiler #define BTUART_INDEX 2 33*cbfa67a1SMarcel Ziswiler #endif 34*cbfa67a1SMarcel Ziswiler 35*cbfa67a1SMarcel Ziswiler /* 36*cbfa67a1SMarcel Ziswiler * Only PXA250 has HWUART, to avoid poluting the code with more macros, 37*cbfa67a1SMarcel Ziswiler * artificially introduce this. 38*cbfa67a1SMarcel Ziswiler */ 39*cbfa67a1SMarcel Ziswiler #ifndef CONFIG_CPU_PXA25X 40*cbfa67a1SMarcel Ziswiler #define HWUART_INDEX 0xff 41*cbfa67a1SMarcel Ziswiler #endif 42*cbfa67a1SMarcel Ziswiler 43*cbfa67a1SMarcel Ziswiler /* 44*cbfa67a1SMarcel Ziswiler * struct pxa_serial_platdata - information about a PXA port 45*cbfa67a1SMarcel Ziswiler * 46*cbfa67a1SMarcel Ziswiler * @base: Uart port base register address 47*cbfa67a1SMarcel Ziswiler * @port: Uart port index, for cpu with pinmux for uart / gpio 48*cbfa67a1SMarcel Ziswiler * baudrtatre: Uart port baudrate 49*cbfa67a1SMarcel Ziswiler */ 50*cbfa67a1SMarcel Ziswiler struct pxa_serial_platdata { 51*cbfa67a1SMarcel Ziswiler struct pxa_uart_regs *base; 52*cbfa67a1SMarcel Ziswiler int port; 53*cbfa67a1SMarcel Ziswiler int baudrate; 54*cbfa67a1SMarcel Ziswiler }; 55*cbfa67a1SMarcel Ziswiler 56*cbfa67a1SMarcel Ziswiler #endif /* __SERIAL_PXA_H */ 57