186256b79SMasahiro Yamada /* 286256b79SMasahiro Yamada * Copyright (c) 2014 Google, Inc 386256b79SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 486256b79SMasahiro Yamada */ 586256b79SMasahiro Yamada 686256b79SMasahiro Yamada #ifndef __serial_pl01x_h 786256b79SMasahiro Yamada #define __serial_pl01x_h 886256b79SMasahiro Yamada 986256b79SMasahiro Yamada enum pl01x_type { 1086256b79SMasahiro Yamada TYPE_PL010, 1186256b79SMasahiro Yamada TYPE_PL011, 1286256b79SMasahiro Yamada }; 1386256b79SMasahiro Yamada 1486256b79SMasahiro Yamada /* 1586256b79SMasahiro Yamada *Information about a serial port 1686256b79SMasahiro Yamada * 1786256b79SMasahiro Yamada * @base: Register base address 1886256b79SMasahiro Yamada * @type: Port type 1986256b79SMasahiro Yamada * @clock: Input clock rate, used for calculating the baud rate divisor 20*cd0fa5bfSEric Anholt * @skip_init: Don't attempt to change port configuration (also means @clock 21*cd0fa5bfSEric Anholt * is ignored) 2286256b79SMasahiro Yamada */ 2386256b79SMasahiro Yamada struct pl01x_serial_platdata { 2486256b79SMasahiro Yamada unsigned long base; 2586256b79SMasahiro Yamada enum pl01x_type type; 2686256b79SMasahiro Yamada unsigned int clock; 27*cd0fa5bfSEric Anholt bool skip_init; 2886256b79SMasahiro Yamada }; 2986256b79SMasahiro Yamada 3086256b79SMasahiro Yamada #endif 31