1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite550x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_P2020 1 20 #define CONFIG_XPEDITE550X 1 21 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 22 #define CONFIG_SYS_FORM_PMC_XMC 1 23 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 24 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 25 #define CONFIG_DISPLAY_BOARDINFO 26 27 #ifndef CONFIG_SYS_TEXT_BASE 28 #define CONFIG_SYS_TEXT_BASE 0xfff80000 29 #endif 30 31 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 32 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ 33 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 34 #define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */ 35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 38 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 39 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 40 #define CONFIG_FSL_ELBC 1 41 42 /* 43 * Multicore config 44 */ 45 #define CONFIG_MP 46 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 47 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 48 49 /* 50 * DDR config 51 */ 52 #define CONFIG_SYS_FSL_DDR3 53 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 54 #define CONFIG_DDR_SPD 55 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 56 #define SPD_EEPROM_ADDRESS 0x54 57 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 58 #define CONFIG_NUM_DDR_CONTROLLERS 1 59 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 60 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 61 #define CONFIG_DDR_ECC 62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 63 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 64 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 65 #define CONFIG_VERY_BIG_RAM 66 67 #ifndef __ASSEMBLY__ 68 extern unsigned long get_board_sys_clk(unsigned long dummy); 69 extern unsigned long get_board_ddr_clk(unsigned long dummy); 70 #endif 71 72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 73 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_L2_CACHE /* toggle L2 cache */ 79 #define CONFIG_BTB /* toggle branch predition */ 80 #define CONFIG_ENABLE_36BIT_PHYS 1 81 82 #define CONFIG_SYS_CCSRBAR 0xef000000 83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 84 85 /* 86 * Diagnostics 87 */ 88 #define CONFIG_SYS_ALT_MEMTEST 89 #define CONFIG_SYS_MEMTEST_START 0x10000000 90 #define CONFIG_SYS_MEMTEST_END 0x20000000 91 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 92 CONFIG_SYS_POST_I2C) 93 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 94 CONFIG_SYS_I2C_LM75_ADDR, \ 95 CONFIG_SYS_I2C_LM90_ADDR, \ 96 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 97 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 98 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 99 CONFIG_SYS_I2C_RTC_ADDR} 100 101 /* 102 * Memory map 103 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 104 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 105 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 106 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 107 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 108 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 109 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 110 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 111 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 112 */ 113 114 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 115 116 /* 117 * NAND flash configuration 118 */ 119 #define CONFIG_SYS_NAND_BASE 0xef800000 120 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 121 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 122 CONFIG_SYS_NAND_BASE2} 123 #define CONFIG_SYS_MAX_NAND_DEVICE 2 124 #define CONFIG_NAND_FSL_ELBC 125 126 /* 127 * NOR flash configuration 128 */ 129 #define CONFIG_SYS_FLASH_BASE 0xf8000000 130 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 131 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 132 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 133 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 134 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 136 #define CONFIG_FLASH_CFI_DRIVER 137 #define CONFIG_SYS_FLASH_CFI 138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 139 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 140 {0xf7f40000, 0xc0000} } 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 142 143 /* 144 * Chip select configuration 145 */ 146 /* NOR Flash 0 on CS0 */ 147 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 148 BR_PS_16 | \ 149 BR_V) 150 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 151 OR_GPCM_CSNT | \ 152 OR_GPCM_XACS | \ 153 OR_GPCM_ACS_DIV2 | \ 154 OR_GPCM_SCY_8 | \ 155 OR_GPCM_TRLX | \ 156 OR_GPCM_EHTR | \ 157 OR_GPCM_EAD) 158 159 /* NOR Flash 1 on CS1 */ 160 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 161 BR_PS_16 | \ 162 BR_V) 163 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 164 165 /* NAND flash on CS2 */ 166 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 167 (2<<BR_DECC_SHIFT) | \ 168 BR_PS_8 | \ 169 BR_MS_FCM | \ 170 BR_V) 171 172 /* NAND flash on CS2 */ 173 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 174 OR_FCM_PGS | \ 175 OR_FCM_CSCT | \ 176 OR_FCM_CST | \ 177 OR_FCM_CHT | \ 178 OR_FCM_SCY_1 | \ 179 OR_FCM_TRLX | \ 180 OR_FCM_EHTR) 181 182 /* NAND flash on CS3 */ 183 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 184 (2<<BR_DECC_SHIFT) | \ 185 BR_PS_8 | \ 186 BR_MS_FCM | \ 187 BR_V) 188 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 189 190 /* 191 * Use L1 as initial stack 192 */ 193 #define CONFIG_SYS_INIT_RAM_LOCK 1 194 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 195 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 196 197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 201 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 202 203 /* 204 * Serial Port 205 */ 206 #define CONFIG_CONS_INDEX 1 207 #define CONFIG_SYS_NS16550_SERIAL 208 #define CONFIG_SYS_NS16550_REG_SIZE 1 209 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 212 #define CONFIG_SYS_BAUDRATE_TABLE \ 213 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 214 #define CONFIG_BAUDRATE 115200 215 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 216 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 217 218 #define CONFIG_FDT_FIXUP_PCI_IRQ 1 219 220 /* 221 * I2C 222 */ 223 #define CONFIG_SYS_I2C 224 #define CONFIG_SYS_I2C_FSL 225 #define CONFIG_SYS_FSL_I2C_SPEED 400000 226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 228 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 229 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 231 232 /* I2C DS7505 temperature sensor */ 233 #define CONFIG_DTT_LM75 234 #define CONFIG_DTT_SENSORS { 0 } 235 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 236 237 /* I2C ADT7461 temperature sensor */ 238 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 239 240 /* I2C EEPROM - AT24C128B */ 241 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 245 246 /* I2C RTC */ 247 #define CONFIG_RTC_M41T11 1 248 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 249 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 250 251 /* GPIO */ 252 #define CONFIG_PCA953X 253 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 254 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 255 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 256 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 257 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 258 259 /* 260 * GPIO pin definitions, PU = pulled high, PD = pulled low 261 */ 262 /* PCA9557 @ 0x18*/ 263 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 264 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 265 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 266 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 267 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 268 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 269 270 /* PCA9557 @ 0x1e*/ 271 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 272 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 273 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 274 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 275 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 276 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 277 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 278 279 /* PCA9557 @ 0x1f */ 280 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 281 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 282 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 283 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 284 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 285 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 286 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 287 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 288 289 /* 290 * General PCI 291 * Memory space is mapped 1-1, but I/O space must start from 0. 292 */ 293 294 /* controller 1 - PEX8112 or XMC, depending on build option */ 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 298 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 299 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 300 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 301 302 303 /* 304 * Networking options 305 */ 306 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 307 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 308 #define CONFIG_TSEC_TBI 309 #define CONFIG_MII 1 /* MII PHY management */ 310 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 311 #define CONFIG_ETHPRIME "eTSEC2" 312 313 /* 314 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 315 * 1000mbps SGMII link 316 */ 317 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 318 TBICR_PHY_RESET \ 319 | TBICR_FULL_DUPLEX \ 320 | TBICR_SPEED1_SET \ 321 ) 322 323 #define CONFIG_TSEC1 1 324 #define CONFIG_TSEC1_NAME "eTSEC1" 325 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 326 #define TSEC1_PHY_ADDR 1 327 #define TSEC1_PHYIDX 0 328 #define CONFIG_HAS_ETH0 329 330 #define CONFIG_TSEC2 1 331 #define CONFIG_TSEC2_NAME "eTSEC2" 332 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 333 #define TSEC2_PHY_ADDR 2 334 #define TSEC2_PHYIDX 0 335 #define CONFIG_HAS_ETH1 336 337 #define CONFIG_TSEC3 1 338 #define CONFIG_TSEC3_NAME "eTSEC3" 339 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 340 #define TSEC3_PHY_ADDR 3 341 #define TSEC3_PHYIDX 0 342 #define CONFIG_HAS_ETH2 343 344 /* 345 * USB 346 */ 347 #define CONFIG_USB_STORAGE 348 #define CONFIG_USB_EHCI 349 #define CONFIG_USB_EHCI_FSL 350 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 351 #define CONFIG_DOS_PARTITION 352 353 /* 354 * Command configuration. 355 */ 356 #define CONFIG_CMD_ASKENV 357 #define CONFIG_CMD_DATE 358 #define CONFIG_CMD_DTT 359 #define CONFIG_CMD_EEPROM 360 #define CONFIG_CMD_JFFS2 361 #define CONFIG_CMD_MII 362 #define CONFIG_CMD_NAND 363 #define CONFIG_CMD_PCA953X 364 #define CONFIG_CMD_PCA953X_INFO 365 #define CONFIG_CMD_PCI 366 #define CONFIG_CMD_PCI_ENUM 367 #define CONFIG_CMD_REGINFO 368 369 /* 370 * Miscellaneous configurable options 371 */ 372 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 373 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 374 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 375 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 376 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 377 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 378 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 379 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 380 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 381 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ 382 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 383 #define CONFIG_PREBOOT /* enable preboot variable */ 384 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 385 386 /* 387 * For booting Linux, the board info and command line data 388 * have to be in the first 16 MB of memory, since this is 389 * the maximum mapped by the Linux kernel during initialization. 390 */ 391 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 392 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 393 394 /* 395 * Environment Configuration 396 */ 397 #define CONFIG_ENV_IS_IN_FLASH 1 398 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 399 #define CONFIG_ENV_SIZE 0x8000 400 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 401 402 /* 403 * Flash memory map: 404 * fff80000 - ffffffff Pri U-Boot (512 KB) 405 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 406 * fff00000 - fff3ffff Pri FDT (256KB) 407 * fef00000 - ffefffff Pri OS image (16MB) 408 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 409 * 410 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 411 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 412 * f7f00000 - f7f3ffff Sec FDT (256KB) 413 * f6f00000 - f7efffff Sec OS image (16MB) 414 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 415 */ 416 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 417 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 418 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 419 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 420 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 421 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 422 423 #define CONFIG_PROG_UBOOT1 \ 424 "$download_cmd $loadaddr $ubootfile; " \ 425 "if test $? -eq 0; then " \ 426 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 427 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 428 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 429 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 430 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 431 "if test $? -ne 0; then " \ 432 "echo PROGRAM FAILED; " \ 433 "else; " \ 434 "echo PROGRAM SUCCEEDED; " \ 435 "fi; " \ 436 "else; " \ 437 "echo DOWNLOAD FAILED; " \ 438 "fi;" 439 440 #define CONFIG_PROG_UBOOT2 \ 441 "$download_cmd $loadaddr $ubootfile; " \ 442 "if test $? -eq 0; then " \ 443 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 444 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 445 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 446 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 447 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 448 "if test $? -ne 0; then " \ 449 "echo PROGRAM FAILED; " \ 450 "else; " \ 451 "echo PROGRAM SUCCEEDED; " \ 452 "fi; " \ 453 "else; " \ 454 "echo DOWNLOAD FAILED; " \ 455 "fi;" 456 457 #define CONFIG_BOOT_OS_NET \ 458 "$download_cmd $osaddr $osfile; " \ 459 "if test $? -eq 0; then " \ 460 "if test -n $fdtaddr; then " \ 461 "$download_cmd $fdtaddr $fdtfile; " \ 462 "if test $? -eq 0; then " \ 463 "bootm $osaddr - $fdtaddr; " \ 464 "else; " \ 465 "echo FDT DOWNLOAD FAILED; " \ 466 "fi; " \ 467 "else; " \ 468 "bootm $osaddr; " \ 469 "fi; " \ 470 "else; " \ 471 "echo OS DOWNLOAD FAILED; " \ 472 "fi;" 473 474 #define CONFIG_PROG_OS1 \ 475 "$download_cmd $osaddr $osfile; " \ 476 "if test $? -eq 0; then " \ 477 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 478 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 479 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 480 "if test $? -ne 0; then " \ 481 "echo OS PROGRAM FAILED; " \ 482 "else; " \ 483 "echo OS PROGRAM SUCCEEDED; " \ 484 "fi; " \ 485 "else; " \ 486 "echo OS DOWNLOAD FAILED; " \ 487 "fi;" 488 489 #define CONFIG_PROG_OS2 \ 490 "$download_cmd $osaddr $osfile; " \ 491 "if test $? -eq 0; then " \ 492 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 493 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 494 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 495 "if test $? -ne 0; then " \ 496 "echo OS PROGRAM FAILED; " \ 497 "else; " \ 498 "echo OS PROGRAM SUCCEEDED; " \ 499 "fi; " \ 500 "else; " \ 501 "echo OS DOWNLOAD FAILED; " \ 502 "fi;" 503 504 #define CONFIG_PROG_FDT1 \ 505 "$download_cmd $fdtaddr $fdtfile; " \ 506 "if test $? -eq 0; then " \ 507 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 508 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 509 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 510 "if test $? -ne 0; then " \ 511 "echo FDT PROGRAM FAILED; " \ 512 "else; " \ 513 "echo FDT PROGRAM SUCCEEDED; " \ 514 "fi; " \ 515 "else; " \ 516 "echo FDT DOWNLOAD FAILED; " \ 517 "fi;" 518 519 #define CONFIG_PROG_FDT2 \ 520 "$download_cmd $fdtaddr $fdtfile; " \ 521 "if test $? -eq 0; then " \ 522 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 523 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 524 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 525 "if test $? -ne 0; then " \ 526 "echo FDT PROGRAM FAILED; " \ 527 "else; " \ 528 "echo FDT PROGRAM SUCCEEDED; " \ 529 "fi; " \ 530 "else; " \ 531 "echo FDT DOWNLOAD FAILED; " \ 532 "fi;" 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "autoload=yes\0" \ 536 "download_cmd=tftp\0" \ 537 "console_args=console=ttyS0,115200\0" \ 538 "root_args=root=/dev/nfs rw\0" \ 539 "misc_args=ip=on\0" \ 540 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 541 "bootfile=/home/user/file\0" \ 542 "osfile=/home/user/board.uImage\0" \ 543 "fdtfile=/home/user/board.dtb\0" \ 544 "ubootfile=/home/user/u-boot.bin\0" \ 545 "fdtaddr=c00000\0" \ 546 "osaddr=0x1000000\0" \ 547 "loadaddr=0x1000000\0" \ 548 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 549 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 550 "prog_os1="CONFIG_PROG_OS1"\0" \ 551 "prog_os2="CONFIG_PROG_OS2"\0" \ 552 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 553 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 554 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 555 "bootcmd_flash1=run set_bootargs; " \ 556 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 557 "bootcmd_flash2=run set_bootargs; " \ 558 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 559 "bootcmd=run bootcmd_flash1\0" 560 #endif /* __CONFIG_H */ 561