1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite550x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_XPEDITE550X 1 18 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 19 #define CONFIG_SYS_FORM_PMC_XMC 1 20 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 22 23 #ifndef CONFIG_SYS_TEXT_BASE 24 #define CONFIG_SYS_TEXT_BASE 0xfff80000 25 #endif 26 27 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 28 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ 29 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 30 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_FSL_ELBC 1 34 35 /* 36 * Multicore config 37 */ 38 #define CONFIG_MP 39 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 40 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 41 42 /* 43 * DDR config 44 */ 45 #define CONFIG_SYS_FSL_DDR3 46 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 47 #define CONFIG_DDR_SPD 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #define SPD_EEPROM_ADDRESS 0x54 50 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 51 #define CONFIG_NUM_DDR_CONTROLLERS 1 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 54 #define CONFIG_DDR_ECC 55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 56 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 57 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 58 #define CONFIG_VERY_BIG_RAM 59 60 #ifndef __ASSEMBLY__ 61 extern unsigned long get_board_sys_clk(unsigned long dummy); 62 extern unsigned long get_board_ddr_clk(unsigned long dummy); 63 #endif 64 65 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 66 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 67 68 /* 69 * These can be toggled for performance analysis, otherwise use default. 70 */ 71 #define CONFIG_L2_CACHE /* toggle L2 cache */ 72 #define CONFIG_BTB /* toggle branch predition */ 73 #define CONFIG_ENABLE_36BIT_PHYS 1 74 75 #define CONFIG_SYS_CCSRBAR 0xef000000 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 78 /* 79 * Diagnostics 80 */ 81 #define CONFIG_SYS_ALT_MEMTEST 82 #define CONFIG_SYS_MEMTEST_START 0x10000000 83 #define CONFIG_SYS_MEMTEST_END 0x20000000 84 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 85 CONFIG_SYS_POST_I2C) 86 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 87 CONFIG_SYS_I2C_LM75_ADDR, \ 88 CONFIG_SYS_I2C_LM90_ADDR, \ 89 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 90 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 91 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 92 CONFIG_SYS_I2C_RTC_ADDR} 93 94 /* 95 * Memory map 96 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 97 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 98 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 99 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 100 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 101 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 102 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 103 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 104 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 105 */ 106 107 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 108 109 /* 110 * NAND flash configuration 111 */ 112 #define CONFIG_SYS_NAND_BASE 0xef800000 113 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 114 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 115 CONFIG_SYS_NAND_BASE2} 116 #define CONFIG_SYS_MAX_NAND_DEVICE 2 117 #define CONFIG_NAND_FSL_ELBC 118 119 /* 120 * NOR flash configuration 121 */ 122 #define CONFIG_SYS_FLASH_BASE 0xf8000000 123 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 124 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 125 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 126 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 127 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 128 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 132 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 133 {0xf7f40000, 0xc0000} } 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 135 136 /* 137 * Chip select configuration 138 */ 139 /* NOR Flash 0 on CS0 */ 140 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 141 BR_PS_16 | \ 142 BR_V) 143 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 144 OR_GPCM_CSNT | \ 145 OR_GPCM_XACS | \ 146 OR_GPCM_ACS_DIV2 | \ 147 OR_GPCM_SCY_8 | \ 148 OR_GPCM_TRLX | \ 149 OR_GPCM_EHTR | \ 150 OR_GPCM_EAD) 151 152 /* NOR Flash 1 on CS1 */ 153 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 154 BR_PS_16 | \ 155 BR_V) 156 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 157 158 /* NAND flash on CS2 */ 159 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 160 (2<<BR_DECC_SHIFT) | \ 161 BR_PS_8 | \ 162 BR_MS_FCM | \ 163 BR_V) 164 165 /* NAND flash on CS2 */ 166 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 167 OR_FCM_PGS | \ 168 OR_FCM_CSCT | \ 169 OR_FCM_CST | \ 170 OR_FCM_CHT | \ 171 OR_FCM_SCY_1 | \ 172 OR_FCM_TRLX | \ 173 OR_FCM_EHTR) 174 175 /* NAND flash on CS3 */ 176 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 177 (2<<BR_DECC_SHIFT) | \ 178 BR_PS_8 | \ 179 BR_MS_FCM | \ 180 BR_V) 181 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 182 183 /* 184 * Use L1 as initial stack 185 */ 186 #define CONFIG_SYS_INIT_RAM_LOCK 1 187 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 188 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 189 190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 192 193 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 194 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 195 196 /* 197 * Serial Port 198 */ 199 #define CONFIG_CONS_INDEX 1 200 #define CONFIG_SYS_NS16550_SERIAL 201 #define CONFIG_SYS_NS16550_REG_SIZE 1 202 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 205 #define CONFIG_SYS_BAUDRATE_TABLE \ 206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 207 #define CONFIG_BAUDRATE 115200 208 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 209 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 210 211 #define CONFIG_FDT_FIXUP_PCI_IRQ 1 212 213 /* 214 * I2C 215 */ 216 #define CONFIG_SYS_I2C 217 #define CONFIG_SYS_I2C_FSL 218 #define CONFIG_SYS_FSL_I2C_SPEED 400000 219 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 220 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 221 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 222 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 223 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 224 225 /* I2C DS7505 temperature sensor */ 226 #define CONFIG_DTT_LM75 227 #define CONFIG_DTT_SENSORS { 0 } 228 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 229 230 /* I2C ADT7461 temperature sensor */ 231 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 232 233 /* I2C EEPROM - AT24C128B */ 234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 238 239 /* I2C RTC */ 240 #define CONFIG_RTC_M41T11 1 241 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 242 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 243 244 /* GPIO */ 245 #define CONFIG_PCA953X 246 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 247 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 248 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 249 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 250 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 251 252 /* 253 * GPIO pin definitions, PU = pulled high, PD = pulled low 254 */ 255 /* PCA9557 @ 0x18*/ 256 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 257 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 258 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 259 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 260 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 261 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 262 263 /* PCA9557 @ 0x1e*/ 264 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 265 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 266 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 267 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 268 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 269 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 270 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 271 272 /* PCA9557 @ 0x1f */ 273 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 274 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 275 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 276 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 277 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 278 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 279 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 280 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 281 282 /* 283 * General PCI 284 * Memory space is mapped 1-1, but I/O space must start from 0. 285 */ 286 287 /* controller 1 - PEX8112 or XMC, depending on build option */ 288 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 289 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 291 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 292 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 293 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 294 295 /* 296 * Networking options 297 */ 298 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 299 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 300 #define CONFIG_TSEC_TBI 301 #define CONFIG_MII 1 /* MII PHY management */ 302 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 303 #define CONFIG_ETHPRIME "eTSEC2" 304 305 /* 306 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 307 * 1000mbps SGMII link 308 */ 309 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 310 TBICR_PHY_RESET \ 311 | TBICR_FULL_DUPLEX \ 312 | TBICR_SPEED1_SET \ 313 ) 314 315 #define CONFIG_TSEC1 1 316 #define CONFIG_TSEC1_NAME "eTSEC1" 317 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 318 #define TSEC1_PHY_ADDR 1 319 #define TSEC1_PHYIDX 0 320 #define CONFIG_HAS_ETH0 321 322 #define CONFIG_TSEC2 1 323 #define CONFIG_TSEC2_NAME "eTSEC2" 324 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 325 #define TSEC2_PHY_ADDR 2 326 #define TSEC2_PHYIDX 0 327 #define CONFIG_HAS_ETH1 328 329 #define CONFIG_TSEC3 1 330 #define CONFIG_TSEC3_NAME "eTSEC3" 331 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 332 #define TSEC3_PHY_ADDR 3 333 #define TSEC3_PHYIDX 0 334 #define CONFIG_HAS_ETH2 335 336 /* 337 * USB 338 */ 339 #define CONFIG_USB_EHCI 340 #define CONFIG_USB_EHCI_FSL 341 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 342 #define CONFIG_DOS_PARTITION 343 344 /* 345 * Command configuration. 346 */ 347 #define CONFIG_CMD_DATE 348 #define CONFIG_CMD_DTT 349 #define CONFIG_CMD_EEPROM 350 #define CONFIG_CMD_JFFS2 351 #define CONFIG_CMD_NAND 352 #define CONFIG_CMD_PCA953X 353 #define CONFIG_CMD_PCA953X_INFO 354 #define CONFIG_CMD_PCI 355 #define CONFIG_CMD_PCI_ENUM 356 #define CONFIG_CMD_REGINFO 357 358 /* 359 * Miscellaneous configurable options 360 */ 361 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 362 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 363 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 364 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 365 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 366 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 367 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 368 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 369 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 370 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 371 #define CONFIG_PREBOOT /* enable preboot variable */ 372 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 373 374 /* 375 * For booting Linux, the board info and command line data 376 * have to be in the first 16 MB of memory, since this is 377 * the maximum mapped by the Linux kernel during initialization. 378 */ 379 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 380 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 381 382 /* 383 * Environment Configuration 384 */ 385 #define CONFIG_ENV_IS_IN_FLASH 1 386 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 387 #define CONFIG_ENV_SIZE 0x8000 388 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 389 390 /* 391 * Flash memory map: 392 * fff80000 - ffffffff Pri U-Boot (512 KB) 393 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 394 * fff00000 - fff3ffff Pri FDT (256KB) 395 * fef00000 - ffefffff Pri OS image (16MB) 396 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 397 * 398 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 399 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 400 * f7f00000 - f7f3ffff Sec FDT (256KB) 401 * f6f00000 - f7efffff Sec OS image (16MB) 402 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 403 */ 404 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 405 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 406 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 407 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 408 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 409 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 410 411 #define CONFIG_PROG_UBOOT1 \ 412 "$download_cmd $loadaddr $ubootfile; " \ 413 "if test $? -eq 0; then " \ 414 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 415 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 416 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 417 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 418 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 419 "if test $? -ne 0; then " \ 420 "echo PROGRAM FAILED; " \ 421 "else; " \ 422 "echo PROGRAM SUCCEEDED; " \ 423 "fi; " \ 424 "else; " \ 425 "echo DOWNLOAD FAILED; " \ 426 "fi;" 427 428 #define CONFIG_PROG_UBOOT2 \ 429 "$download_cmd $loadaddr $ubootfile; " \ 430 "if test $? -eq 0; then " \ 431 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 432 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 433 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 434 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 435 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 436 "if test $? -ne 0; then " \ 437 "echo PROGRAM FAILED; " \ 438 "else; " \ 439 "echo PROGRAM SUCCEEDED; " \ 440 "fi; " \ 441 "else; " \ 442 "echo DOWNLOAD FAILED; " \ 443 "fi;" 444 445 #define CONFIG_BOOT_OS_NET \ 446 "$download_cmd $osaddr $osfile; " \ 447 "if test $? -eq 0; then " \ 448 "if test -n $fdtaddr; then " \ 449 "$download_cmd $fdtaddr $fdtfile; " \ 450 "if test $? -eq 0; then " \ 451 "bootm $osaddr - $fdtaddr; " \ 452 "else; " \ 453 "echo FDT DOWNLOAD FAILED; " \ 454 "fi; " \ 455 "else; " \ 456 "bootm $osaddr; " \ 457 "fi; " \ 458 "else; " \ 459 "echo OS DOWNLOAD FAILED; " \ 460 "fi;" 461 462 #define CONFIG_PROG_OS1 \ 463 "$download_cmd $osaddr $osfile; " \ 464 "if test $? -eq 0; then " \ 465 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 466 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 467 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 468 "if test $? -ne 0; then " \ 469 "echo OS PROGRAM FAILED; " \ 470 "else; " \ 471 "echo OS PROGRAM SUCCEEDED; " \ 472 "fi; " \ 473 "else; " \ 474 "echo OS DOWNLOAD FAILED; " \ 475 "fi;" 476 477 #define CONFIG_PROG_OS2 \ 478 "$download_cmd $osaddr $osfile; " \ 479 "if test $? -eq 0; then " \ 480 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 481 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 482 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 483 "if test $? -ne 0; then " \ 484 "echo OS PROGRAM FAILED; " \ 485 "else; " \ 486 "echo OS PROGRAM SUCCEEDED; " \ 487 "fi; " \ 488 "else; " \ 489 "echo OS DOWNLOAD FAILED; " \ 490 "fi;" 491 492 #define CONFIG_PROG_FDT1 \ 493 "$download_cmd $fdtaddr $fdtfile; " \ 494 "if test $? -eq 0; then " \ 495 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 496 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 497 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 498 "if test $? -ne 0; then " \ 499 "echo FDT PROGRAM FAILED; " \ 500 "else; " \ 501 "echo FDT PROGRAM SUCCEEDED; " \ 502 "fi; " \ 503 "else; " \ 504 "echo FDT DOWNLOAD FAILED; " \ 505 "fi;" 506 507 #define CONFIG_PROG_FDT2 \ 508 "$download_cmd $fdtaddr $fdtfile; " \ 509 "if test $? -eq 0; then " \ 510 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 511 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 512 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 513 "if test $? -ne 0; then " \ 514 "echo FDT PROGRAM FAILED; " \ 515 "else; " \ 516 "echo FDT PROGRAM SUCCEEDED; " \ 517 "fi; " \ 518 "else; " \ 519 "echo FDT DOWNLOAD FAILED; " \ 520 "fi;" 521 522 #define CONFIG_EXTRA_ENV_SETTINGS \ 523 "autoload=yes\0" \ 524 "download_cmd=tftp\0" \ 525 "console_args=console=ttyS0,115200\0" \ 526 "root_args=root=/dev/nfs rw\0" \ 527 "misc_args=ip=on\0" \ 528 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 529 "bootfile=/home/user/file\0" \ 530 "osfile=/home/user/board.uImage\0" \ 531 "fdtfile=/home/user/board.dtb\0" \ 532 "ubootfile=/home/user/u-boot.bin\0" \ 533 "fdtaddr=0x1e00000\0" \ 534 "osaddr=0x1000000\0" \ 535 "loadaddr=0x1000000\0" \ 536 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 537 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 538 "prog_os1="CONFIG_PROG_OS1"\0" \ 539 "prog_os2="CONFIG_PROG_OS2"\0" \ 540 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 541 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 542 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 543 "bootcmd_flash1=run set_bootargs; " \ 544 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 545 "bootcmd_flash2=run set_bootargs; " \ 546 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 547 "bootcmd=run bootcmd_flash1\0" 548 #endif /* __CONFIG_H */ 549