1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite537x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_SYS_BOARD_NAME "XPedite5370" 18 #define CONFIG_SYS_FORM_3U_VPX 1 19 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 20 21 #ifndef CONFIG_SYS_TEXT_BASE 22 #define CONFIG_SYS_TEXT_BASE 0xfff80000 23 #endif 24 25 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 26 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 27 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 32 33 /* 34 * Multicore config 35 */ 36 #define CONFIG_MP 37 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 38 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 39 40 /* 41 * DDR config 42 */ 43 #undef CONFIG_FSL_DDR_INTERACTIVE 44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 45 #define CONFIG_DDR_SPD 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 48 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 49 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 51 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 52 #define CONFIG_DDR_ECC 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 56 #define CONFIG_VERY_BIG_RAM 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_board_sys_clk(unsigned long dummy); 60 extern unsigned long get_board_ddr_clk(unsigned long dummy); 61 #endif 62 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 #define CONFIG_ENABLE_36BIT_PHYS 1 72 73 #define CONFIG_SYS_CCSRBAR 0xef000000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* 77 * Diagnostics 78 */ 79 #define CONFIG_SYS_ALT_MEMTEST 80 #define CONFIG_SYS_MEMTEST_START 0x10000000 81 #define CONFIG_SYS_MEMTEST_END 0x20000000 82 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 83 CONFIG_SYS_POST_I2C) 84 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ 85 #define I2C_ADDR_IGNORE_LIST {0x50} 86 87 /* 88 * Memory map 89 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 90 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 91 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 92 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 93 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 94 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 95 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 96 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 97 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 98 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 99 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 100 */ 101 102 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 103 104 /* 105 * NAND flash configuration 106 */ 107 #define CONFIG_SYS_NAND_BASE 0xef800000 108 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 109 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 110 CONFIG_SYS_NAND_BASE2} 111 #define CONFIG_SYS_MAX_NAND_DEVICE 2 112 #define CONFIG_NAND_FSL_ELBC 113 114 /* 115 * NOR flash configuration 116 */ 117 #define CONFIG_SYS_FLASH_BASE 0xf8000000 118 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 119 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 120 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 121 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 122 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 123 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 124 #define CONFIG_FLASH_CFI_DRIVER 125 #define CONFIG_SYS_FLASH_CFI 126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 127 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 128 {0xf7f40000, 0xc0000} } 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 131 /* 132 * Chip select configuration 133 */ 134 /* NOR Flash 0 on CS0 */ 135 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 136 BR_PS_16 | \ 137 BR_V) 138 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 139 OR_GPCM_CSNT | \ 140 OR_GPCM_XACS | \ 141 OR_GPCM_ACS_DIV2 | \ 142 OR_GPCM_SCY_8 | \ 143 OR_GPCM_TRLX | \ 144 OR_GPCM_EHTR | \ 145 OR_GPCM_EAD) 146 147 /* NOR Flash 1 on CS1 */ 148 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 149 BR_PS_16 | \ 150 BR_V) 151 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 152 153 /* NAND flash on CS2 */ 154 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 155 (2<<BR_DECC_SHIFT) | \ 156 BR_PS_8 | \ 157 BR_MS_FCM | \ 158 BR_V) 159 160 /* NAND flash on CS2 */ 161 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 162 OR_FCM_PGS | \ 163 OR_FCM_CSCT | \ 164 OR_FCM_CST | \ 165 OR_FCM_CHT | \ 166 OR_FCM_SCY_1 | \ 167 OR_FCM_TRLX | \ 168 OR_FCM_EHTR) 169 170 /* NAND flash on CS3 */ 171 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 172 (2<<BR_DECC_SHIFT) | \ 173 BR_PS_8 | \ 174 BR_MS_FCM | \ 175 BR_V) 176 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 177 178 /* 179 * Use L1 as initial stack 180 */ 181 #define CONFIG_SYS_INIT_RAM_LOCK 1 182 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 184 185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 187 188 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 189 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 190 191 /* 192 * Serial Port 193 */ 194 #define CONFIG_CONS_INDEX 1 195 #define CONFIG_SYS_NS16550_SERIAL 196 #define CONFIG_SYS_NS16550_REG_SIZE 1 197 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 200 #define CONFIG_SYS_BAUDRATE_TABLE \ 201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 202 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 203 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 204 205 /* 206 * I2C 207 */ 208 #define CONFIG_SYS_I2C 209 #define CONFIG_SYS_I2C_FSL 210 #define CONFIG_SYS_FSL_I2C_SPEED 400000 211 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 213 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 216 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 217 218 /* PEX8518 slave I2C interface */ 219 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 220 221 /* I2C DS1631 temperature sensor */ 222 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 223 224 /* I2C EEPROM - AT24C128B */ 225 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 226 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 229 230 /* I2C RTC */ 231 #define CONFIG_RTC_M41T11 1 232 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 233 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 234 235 /* GPIO/EEPROM/SRAM */ 236 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 237 238 /* GPIO */ 239 #define CONFIG_PCA953X 240 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 241 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 242 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 243 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 244 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 245 246 /* 247 * PU = pulled high, PD = pulled low 248 * I = input, O = output, IO = input/output 249 */ 250 /* PCA9557 @ 0x18*/ 251 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 252 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 253 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 254 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 255 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 256 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 257 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ 258 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ 259 260 /* PCA9557 @ 0x1c*/ 261 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 262 #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ 263 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 264 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 265 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 266 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 267 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 268 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 269 270 /* PCA9557 @ 0x1e*/ 271 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 272 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 273 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 274 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 275 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 276 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ 277 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ 278 279 /* PCA9557 @ 0x1f */ 280 #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ 281 #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ 282 #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ 283 #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ 284 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ 285 286 /* 287 * General PCI 288 * Memory space is mapped 1-1, but I/O space must start from 0. 289 */ 290 /* PCIE1 - VPX P1 */ 291 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 292 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 293 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 294 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 295 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 296 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 297 298 /* PCIE2 - PEX8518 */ 299 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 300 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 301 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 302 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 303 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 304 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 305 306 /* 307 * Networking options 308 */ 309 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 310 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 311 #define CONFIG_TSEC_TBI 312 #define CONFIG_MII 1 /* MII PHY management */ 313 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 314 #define CONFIG_ETHPRIME "eTSEC2" 315 316 /* 317 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 318 * 1000mbps SGMII link 319 */ 320 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 321 TBICR_PHY_RESET \ 322 | TBICR_FULL_DUPLEX \ 323 | TBICR_SPEED1_SET \ 324 ) 325 326 #define CONFIG_TSEC1 1 327 #define CONFIG_TSEC1_NAME "eTSEC1" 328 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 329 #define TSEC1_PHY_ADDR 1 330 #define TSEC1_PHYIDX 0 331 #define CONFIG_HAS_ETH0 332 333 #define CONFIG_TSEC2 1 334 #define CONFIG_TSEC2_NAME "eTSEC2" 335 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 336 #define TSEC2_PHY_ADDR 2 337 #define TSEC2_PHYIDX 0 338 #define CONFIG_HAS_ETH1 339 340 /* 341 * Command configuration. 342 */ 343 #define CONFIG_CMD_EEPROM 344 #define CONFIG_CMD_JFFS2 345 #define CONFIG_CMD_NAND 346 #define CONFIG_CMD_PCA953X 347 #define CONFIG_CMD_PCA953X_INFO 348 #define CONFIG_CMD_PCI 349 #define CONFIG_CMD_PCI_ENUM 350 #define CONFIG_CMD_REGINFO 351 352 /* 353 * Miscellaneous configurable options 354 */ 355 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 356 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 357 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 358 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 359 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 360 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 361 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 362 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 363 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 364 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 365 #define CONFIG_PREBOOT /* enable preboot variable */ 366 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 367 368 /* 369 * For booting Linux, the board info and command line data 370 * have to be in the first 16 MB of memory, since this is 371 * the maximum mapped by the Linux kernel during initialization. 372 */ 373 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 374 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 375 376 /* 377 * Environment Configuration 378 */ 379 #define CONFIG_ENV_IS_IN_FLASH 1 380 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 381 #define CONFIG_ENV_SIZE 0x8000 382 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 383 384 /* 385 * Flash memory map: 386 * fff80000 - ffffffff Pri U-Boot (512 KB) 387 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 388 * fff00000 - fff3ffff Pri FDT (256KB) 389 * fef00000 - ffefffff Pri OS image (16MB) 390 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 391 * 392 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 393 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 394 * f7f00000 - f7f3ffff Sec FDT (256KB) 395 * f6f00000 - f7efffff Sec OS image (16MB) 396 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 397 */ 398 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 399 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 400 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 401 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 402 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 403 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 404 405 #define CONFIG_PROG_UBOOT1 \ 406 "$download_cmd $loadaddr $ubootfile; " \ 407 "if test $? -eq 0; then " \ 408 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 409 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 410 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 411 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 412 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 413 "if test $? -ne 0; then " \ 414 "echo PROGRAM FAILED; " \ 415 "else; " \ 416 "echo PROGRAM SUCCEEDED; " \ 417 "fi; " \ 418 "else; " \ 419 "echo DOWNLOAD FAILED; " \ 420 "fi;" 421 422 #define CONFIG_PROG_UBOOT2 \ 423 "$download_cmd $loadaddr $ubootfile; " \ 424 "if test $? -eq 0; then " \ 425 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 426 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 427 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 428 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 429 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 430 "if test $? -ne 0; then " \ 431 "echo PROGRAM FAILED; " \ 432 "else; " \ 433 "echo PROGRAM SUCCEEDED; " \ 434 "fi; " \ 435 "else; " \ 436 "echo DOWNLOAD FAILED; " \ 437 "fi;" 438 439 #define CONFIG_BOOT_OS_NET \ 440 "$download_cmd $osaddr $osfile; " \ 441 "if test $? -eq 0; then " \ 442 "if test -n $fdtaddr; then " \ 443 "$download_cmd $fdtaddr $fdtfile; " \ 444 "if test $? -eq 0; then " \ 445 "bootm $osaddr - $fdtaddr; " \ 446 "else; " \ 447 "echo FDT DOWNLOAD FAILED; " \ 448 "fi; " \ 449 "else; " \ 450 "bootm $osaddr; " \ 451 "fi; " \ 452 "else; " \ 453 "echo OS DOWNLOAD FAILED; " \ 454 "fi;" 455 456 #define CONFIG_PROG_OS1 \ 457 "$download_cmd $osaddr $osfile; " \ 458 "if test $? -eq 0; then " \ 459 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 460 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 461 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 462 "if test $? -ne 0; then " \ 463 "echo OS PROGRAM FAILED; " \ 464 "else; " \ 465 "echo OS PROGRAM SUCCEEDED; " \ 466 "fi; " \ 467 "else; " \ 468 "echo OS DOWNLOAD FAILED; " \ 469 "fi;" 470 471 #define CONFIG_PROG_OS2 \ 472 "$download_cmd $osaddr $osfile; " \ 473 "if test $? -eq 0; then " \ 474 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 475 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 476 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 477 "if test $? -ne 0; then " \ 478 "echo OS PROGRAM FAILED; " \ 479 "else; " \ 480 "echo OS PROGRAM SUCCEEDED; " \ 481 "fi; " \ 482 "else; " \ 483 "echo OS DOWNLOAD FAILED; " \ 484 "fi;" 485 486 #define CONFIG_PROG_FDT1 \ 487 "$download_cmd $fdtaddr $fdtfile; " \ 488 "if test $? -eq 0; then " \ 489 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 490 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 491 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 492 "if test $? -ne 0; then " \ 493 "echo FDT PROGRAM FAILED; " \ 494 "else; " \ 495 "echo FDT PROGRAM SUCCEEDED; " \ 496 "fi; " \ 497 "else; " \ 498 "echo FDT DOWNLOAD FAILED; " \ 499 "fi;" 500 501 #define CONFIG_PROG_FDT2 \ 502 "$download_cmd $fdtaddr $fdtfile; " \ 503 "if test $? -eq 0; then " \ 504 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 505 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 506 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 507 "if test $? -ne 0; then " \ 508 "echo FDT PROGRAM FAILED; " \ 509 "else; " \ 510 "echo FDT PROGRAM SUCCEEDED; " \ 511 "fi; " \ 512 "else; " \ 513 "echo FDT DOWNLOAD FAILED; " \ 514 "fi;" 515 516 #define CONFIG_EXTRA_ENV_SETTINGS \ 517 "autoload=yes\0" \ 518 "download_cmd=tftp\0" \ 519 "console_args=console=ttyS0,115200\0" \ 520 "root_args=root=/dev/nfs rw\0" \ 521 "misc_args=ip=on\0" \ 522 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 523 "bootfile=/home/user/file\0" \ 524 "osfile=/home/user/board.uImage\0" \ 525 "fdtfile=/home/user/board.dtb\0" \ 526 "ubootfile=/home/user/u-boot.bin\0" \ 527 "fdtaddr=0x1e00000\0" \ 528 "osaddr=0x1000000\0" \ 529 "loadaddr=0x1000000\0" \ 530 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 531 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 532 "prog_os1="CONFIG_PROG_OS1"\0" \ 533 "prog_os2="CONFIG_PROG_OS2"\0" \ 534 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 535 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 536 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 537 "bootcmd_flash1=run set_bootargs; " \ 538 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 539 "bootcmd_flash2=run set_bootargs; " \ 540 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 541 "bootcmd=run bootcmd_flash1\0" 542 #endif /* __CONFIG_H */ 543