1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite520x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_XPEDITE5200 1 18 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 19 #define CONFIG_SYS_FORM_PMC_XMC 1 20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 21 22 #ifndef CONFIG_SYS_TEXT_BASE 23 #define CONFIG_SYS_TEXT_BASE 0xfff80000 24 #endif 25 26 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 27 #define CONFIG_PCI1 1 /* PCI controller 1 */ 28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 32 /* 33 * DDR config 34 */ 35 #define CONFIG_SYS_FSL_DDR2 36 #undef CONFIG_FSL_DDR_INTERACTIVE 37 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 38 #define CONFIG_DDR_SPD 39 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 40 #define SPD_EEPROM_ADDRESS 0x54 41 #define CONFIG_NUM_DDR_CONTROLLERS 1 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 44 #define CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_VERY_BIG_RAM 49 50 #define CONFIG_SYS_CLK_FREQ 66666666 51 52 /* 53 * These can be toggled for performance analysis, otherwise use default. 54 */ 55 #define CONFIG_L2_CACHE /* toggle L2 cache */ 56 #define CONFIG_BTB /* toggle branch predition */ 57 #define CONFIG_ENABLE_36BIT_PHYS 1 58 59 #define CONFIG_SYS_CCSRBAR 0xef000000 60 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 61 62 /* 63 * Diagnostics 64 */ 65 #define CONFIG_SYS_ALT_MEMTEST 66 #define CONFIG_SYS_MEMTEST_START 0x10000000 67 #define CONFIG_SYS_MEMTEST_END 0x20000000 68 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 69 CONFIG_SYS_POST_I2C) 70 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 71 CONFIG_SYS_I2C_EEPROM_ADDR, \ 72 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 73 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 74 CONFIG_SYS_I2C_RTC_ADDR} 75 76 /* 77 * Memory map 78 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 79 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 80 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 81 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 82 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 83 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 84 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 85 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 86 */ 87 88 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 89 90 /* 91 * NAND flash configuration 92 */ 93 #define CONFIG_SYS_NAND_BASE 0xef800000 94 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 95 #define CONFIG_SYS_MAX_NAND_DEVICE 1 96 #define CONFIG_NAND_ACTL 97 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 98 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 99 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 100 #define CONFIG_SYS_NAND_ACTL_DELAY 25 101 102 /* 103 * NOR flash configuration 104 */ 105 #define CONFIG_SYS_FLASH_BASE 0xfc000000 106 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 107 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_CFI 114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 115 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 116 {0xfbf40000, 0xc0000} } 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 118 119 /* 120 * Chip select configuration 121 */ 122 /* NOR Flash 0 on CS0 */ 123 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 124 BR_PS_16 | \ 125 BR_V) 126 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 127 OR_GPCM_ACS_DIV4 | \ 128 OR_GPCM_SCY_8) 129 130 /* NOR Flash 1 on CS1 */ 131 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 132 BR_PS_16 | \ 133 BR_V) 134 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 135 136 /* NAND flash on CS2 */ 137 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 138 BR_PS_8 | \ 139 BR_V) 140 141 /* NAND flash on CS2 */ 142 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 143 OR_GPCM_BCTLD | \ 144 OR_GPCM_CSNT | \ 145 OR_GPCM_ACS_DIV4 | \ 146 OR_GPCM_SCY_4 | \ 147 OR_GPCM_TRLX | \ 148 OR_GPCM_EHTR) 149 150 /* NAND flash on CS3 */ 151 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 152 BR_PS_8 | \ 153 BR_V) 154 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 155 156 /* 157 * Use L1 as initial stack 158 */ 159 #define CONFIG_SYS_INIT_RAM_LOCK 1 160 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 161 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 162 163 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 165 166 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 167 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 168 169 /* 170 * Serial Port 171 */ 172 #define CONFIG_CONS_INDEX 1 173 #define CONFIG_SYS_NS16550_SERIAL 174 #define CONFIG_SYS_NS16550_REG_SIZE 1 175 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 176 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 177 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 178 #define CONFIG_SYS_BAUDRATE_TABLE \ 179 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 180 #define CONFIG_BAUDRATE 115200 181 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 182 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 183 184 /* 185 * I2C 186 */ 187 #define CONFIG_SYS_I2C 188 #define CONFIG_SYS_I2C_FSL 189 #define CONFIG_SYS_FSL_I2C_SPEED 400000 190 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 191 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 192 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 193 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 194 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 195 196 /* I2C EEPROM */ 197 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 198 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 199 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 201 202 /* I2C RTC */ 203 #define CONFIG_RTC_M41T11 1 204 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 205 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 206 207 /* GPIO */ 208 #define CONFIG_PCA953X 209 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 210 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 211 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 212 213 /* PCA957 @ 0x18 */ 214 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 215 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 216 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 217 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 218 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 219 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 220 #define CONFIG_SYS_PCA953X_MONARCH 0x40 221 #define CONFIG_SYS_PCA953X_EREADY 0x80 222 223 /* PCA957 @ 0x19 */ 224 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 225 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 226 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 227 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 228 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 229 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 230 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 231 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 232 233 /* 12-bit ADC used to measure CPU diode */ 234 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 235 236 /* 237 * General PCI 238 * Memory space is mapped 1-1, but I/O space must start from 0. 239 */ 240 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 241 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 242 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 243 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 244 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 245 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 246 247 /* 248 * Networking options 249 */ 250 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 251 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 252 #define CONFIG_MII 1 /* MII PHY management */ 253 #define CONFIG_ETHPRIME "eTSEC1" 254 255 #define CONFIG_TSEC1 1 256 #define CONFIG_TSEC1_NAME "eTSEC1" 257 #define TSEC1_FLAGS TSEC_GIGABIT 258 #define TSEC1_PHY_ADDR 1 259 #define TSEC1_PHYIDX 0 260 #define CONFIG_HAS_ETH0 261 262 #define CONFIG_TSEC2 1 263 #define CONFIG_TSEC2_NAME "eTSEC2" 264 #define TSEC2_FLAGS TSEC_GIGABIT 265 #define TSEC2_PHY_ADDR 2 266 #define TSEC2_PHYIDX 0 267 #define CONFIG_HAS_ETH1 268 269 #define CONFIG_TSEC3 1 270 #define CONFIG_TSEC3_NAME "eTSEC3" 271 #define TSEC3_FLAGS TSEC_GIGABIT 272 #define TSEC3_PHY_ADDR 3 273 #define TSEC3_PHYIDX 0 274 #define CONFIG_HAS_ETH2 275 276 #define CONFIG_TSEC4 1 277 #define CONFIG_TSEC4_NAME "eTSEC4" 278 #define TSEC4_FLAGS TSEC_GIGABIT 279 #define TSEC4_PHY_ADDR 4 280 #define TSEC4_PHYIDX 0 281 #define CONFIG_HAS_ETH3 282 283 /* 284 * BOOTP options 285 */ 286 #define CONFIG_BOOTP_BOOTFILESIZE 287 #define CONFIG_BOOTP_BOOTPATH 288 #define CONFIG_BOOTP_GATEWAY 289 290 /* 291 * Command configuration. 292 */ 293 #define CONFIG_CMD_DATE 294 #define CONFIG_CMD_EEPROM 295 #define CONFIG_CMD_JFFS2 296 #define CONFIG_CMD_NAND 297 #define CONFIG_CMD_PCA953X 298 #define CONFIG_CMD_PCA953X_INFO 299 #define CONFIG_CMD_PCI 300 #define CONFIG_CMD_PCI_ENUM 301 #define CONFIG_CMD_REGINFO 302 303 /* 304 * Miscellaneous configurable options 305 */ 306 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 307 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 308 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 309 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 310 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 311 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 312 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 313 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 314 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 315 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 316 #define CONFIG_PREBOOT /* enable preboot variable */ 317 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 318 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 319 320 /* 321 * For booting Linux, the board info and command line data 322 * have to be in the first 16 MB of memory, since this is 323 * the maximum mapped by the Linux kernel during initialization. 324 */ 325 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 326 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 327 328 /* 329 * Environment Configuration 330 */ 331 #define CONFIG_ENV_IS_IN_FLASH 1 332 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 333 #define CONFIG_ENV_SIZE 0x8000 334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 335 336 /* 337 * Flash memory map: 338 * fff80000 - ffffffff Pri U-Boot (512 KB) 339 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 340 * fff00000 - fff3ffff Pri FDT (256KB) 341 * fef00000 - ffefffff Pri OS image (16MB) 342 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 343 * 344 * fbf80000 - fbffffff Sec U-Boot (512 KB) 345 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 346 * fbf00000 - fbf3ffff Sec FDT (256KB) 347 * faf00000 - fbefffff Sec OS image (16MB) 348 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 349 */ 350 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 351 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) 352 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 353 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) 354 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 355 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) 356 357 #define CONFIG_PROG_UBOOT1 \ 358 "$download_cmd $loadaddr $ubootfile; " \ 359 "if test $? -eq 0; then " \ 360 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 361 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 362 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 363 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 364 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 365 "if test $? -ne 0; then " \ 366 "echo PROGRAM FAILED; " \ 367 "else; " \ 368 "echo PROGRAM SUCCEEDED; " \ 369 "fi; " \ 370 "else; " \ 371 "echo DOWNLOAD FAILED; " \ 372 "fi;" 373 374 #define CONFIG_PROG_UBOOT2 \ 375 "$download_cmd $loadaddr $ubootfile; " \ 376 "if test $? -eq 0; then " \ 377 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 378 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 379 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 380 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 381 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 382 "if test $? -ne 0; then " \ 383 "echo PROGRAM FAILED; " \ 384 "else; " \ 385 "echo PROGRAM SUCCEEDED; " \ 386 "fi; " \ 387 "else; " \ 388 "echo DOWNLOAD FAILED; " \ 389 "fi;" 390 391 #define CONFIG_BOOT_OS_NET \ 392 "$download_cmd $osaddr $osfile; " \ 393 "if test $? -eq 0; then " \ 394 "if test -n $fdtaddr; then " \ 395 "$download_cmd $fdtaddr $fdtfile; " \ 396 "if test $? -eq 0; then " \ 397 "bootm $osaddr - $fdtaddr; " \ 398 "else; " \ 399 "echo FDT DOWNLOAD FAILED; " \ 400 "fi; " \ 401 "else; " \ 402 "bootm $osaddr; " \ 403 "fi; " \ 404 "else; " \ 405 "echo OS DOWNLOAD FAILED; " \ 406 "fi;" 407 408 #define CONFIG_PROG_OS1 \ 409 "$download_cmd $osaddr $osfile; " \ 410 "if test $? -eq 0; then " \ 411 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 412 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 413 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 414 "if test $? -ne 0; then " \ 415 "echo OS PROGRAM FAILED; " \ 416 "else; " \ 417 "echo OS PROGRAM SUCCEEDED; " \ 418 "fi; " \ 419 "else; " \ 420 "echo OS DOWNLOAD FAILED; " \ 421 "fi;" 422 423 #define CONFIG_PROG_OS2 \ 424 "$download_cmd $osaddr $osfile; " \ 425 "if test $? -eq 0; then " \ 426 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 427 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 428 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 429 "if test $? -ne 0; then " \ 430 "echo OS PROGRAM FAILED; " \ 431 "else; " \ 432 "echo OS PROGRAM SUCCEEDED; " \ 433 "fi; " \ 434 "else; " \ 435 "echo OS DOWNLOAD FAILED; " \ 436 "fi;" 437 438 #define CONFIG_PROG_FDT1 \ 439 "$download_cmd $fdtaddr $fdtfile; " \ 440 "if test $? -eq 0; then " \ 441 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 442 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 443 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 444 "if test $? -ne 0; then " \ 445 "echo FDT PROGRAM FAILED; " \ 446 "else; " \ 447 "echo FDT PROGRAM SUCCEEDED; " \ 448 "fi; " \ 449 "else; " \ 450 "echo FDT DOWNLOAD FAILED; " \ 451 "fi;" 452 453 #define CONFIG_PROG_FDT2 \ 454 "$download_cmd $fdtaddr $fdtfile; " \ 455 "if test $? -eq 0; then " \ 456 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 457 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 458 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 459 "if test $? -ne 0; then " \ 460 "echo FDT PROGRAM FAILED; " \ 461 "else; " \ 462 "echo FDT PROGRAM SUCCEEDED; " \ 463 "fi; " \ 464 "else; " \ 465 "echo FDT DOWNLOAD FAILED; " \ 466 "fi;" 467 468 #define CONFIG_EXTRA_ENV_SETTINGS \ 469 "autoload=yes\0" \ 470 "download_cmd=tftp\0" \ 471 "console_args=console=ttyS0,115200\0" \ 472 "root_args=root=/dev/nfs rw\0" \ 473 "misc_args=ip=on\0" \ 474 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 475 "bootfile=/home/user/file\0" \ 476 "osfile=/home/user/board.uImage\0" \ 477 "fdtfile=/home/user/board.dtb\0" \ 478 "ubootfile=/home/user/u-boot.bin\0" \ 479 "fdtaddr=0x1e00000\0" \ 480 "osaddr=0x1000000\0" \ 481 "loadaddr=0x1000000\0" \ 482 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 483 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 484 "prog_os1="CONFIG_PROG_OS1"\0" \ 485 "prog_os2="CONFIG_PROG_OS2"\0" \ 486 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 487 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 488 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 489 "bootcmd_flash1=run set_bootargs; " \ 490 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 491 "bootcmd_flash2=run set_bootargs; " \ 492 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 493 "bootcmd=run bootcmd_flash1\0" 494 #endif /* __CONFIG_H */ 495