1 /* 2 * Copyright 2009 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite517x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ 18 #define CONFIG_SYS_BOARD_NAME "XPedite5170" 19 #define CONFIG_SYS_FORM_3U_VPX 1 20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 22 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 23 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 24 #define CONFIG_ALTIVEC 1 25 26 #define CONFIG_SYS_TEXT_BASE 0xfff00000 27 28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 29 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 30 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 35 /* 36 * DDR config 37 */ 38 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 39 #define CONFIG_DDR_SPD 40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 41 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 42 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 45 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 46 #define CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 50 #define CONFIG_VERY_BIG_RAM 51 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 52 53 /* 54 * virtual address to be used for temporary mappings. There 55 * should be 128k free at this VA. 56 */ 57 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_board_sys_clk(unsigned long dummy); 61 #endif 62 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ 64 65 /* 66 * L2CR setup 67 */ 68 #define CONFIG_SYS_L2 69 #define L2_INIT 0 70 #define L2_ENABLE (L2CR_L2E) 71 72 /* 73 * Base addresses -- Note these are effective addresses where the 74 * actual resources get mapped (not physical addresses) 75 */ 76 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ 77 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 81 82 /* 83 * Diagnostics 84 */ 85 #define CONFIG_SYS_ALT_MEMTEST 86 #define CONFIG_SYS_MEMTEST_START 0x10000000 87 #define CONFIG_SYS_MEMTEST_END 0x20000000 88 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ 89 CONFIG_SYS_POST_I2C) 90 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ 91 #define I2C_ADDR_IGNORE_LIST {0x50} 92 93 /* 94 * Memory map 95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 96 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 97 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 98 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 99 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 100 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 101 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 102 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 103 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 104 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 105 */ 106 107 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) 108 109 /* 110 * NAND flash configuration 111 */ 112 #define CONFIG_SYS_NAND_BASE 0xef800000 113 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 114 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} 115 #define CONFIG_SYS_MAX_NAND_DEVICE 2 116 #define CONFIG_NAND_ACTL 117 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ 118 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ 119 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ 120 #define CONFIG_SYS_NAND_ACTL_DELAY 25 121 #define CONFIG_JFFS2_NAND 122 123 /* 124 * NOR flash configuration 125 */ 126 #define CONFIG_SYS_FLASH_BASE 0xf8000000 127 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 128 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 129 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 130 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 131 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 132 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 133 #define CONFIG_FLASH_CFI_DRIVER 134 #define CONFIG_SYS_FLASH_CFI 135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 136 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ 137 {0xf7f00000, 0xc0000} } 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 139 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 140 141 /* 142 * Chip select configuration 143 */ 144 /* NOR Flash 0 on CS0 */ 145 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 146 BR_PS_16 |\ 147 BR_V) 148 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ 149 OR_GPCM_CSNT |\ 150 OR_GPCM_XACS |\ 151 OR_GPCM_ACS_DIV2 |\ 152 OR_GPCM_SCY_8 |\ 153 OR_GPCM_TRLX |\ 154 OR_GPCM_EHTR |\ 155 OR_GPCM_EAD) 156 157 /* NOR Flash 1 on CS1 */ 158 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ 159 BR_PS_16 |\ 160 BR_V) 161 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 162 163 /* NAND flash on CS2 */ 164 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ 165 BR_PS_8 |\ 166 BR_V) 167 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ 168 OR_GPCM_BCTLD |\ 169 OR_GPCM_CSNT |\ 170 OR_GPCM_ACS_DIV4 |\ 171 OR_GPCM_SCY_4 |\ 172 OR_GPCM_TRLX |\ 173 OR_GPCM_EHTR) 174 175 /* Optional NAND flash on CS3 */ 176 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ 177 BR_PS_8 |\ 178 BR_V) 179 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 180 181 /* 182 * Use L1 as initial stack 183 */ 184 #define CONFIG_SYS_INIT_RAM_LOCK 1 185 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 186 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 187 188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 189 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 190 191 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 192 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 193 194 /* 195 * Serial Port 196 */ 197 #define CONFIG_CONS_INDEX 1 198 #define CONFIG_SYS_NS16550_SERIAL 199 #define CONFIG_SYS_NS16550_REG_SIZE 1 200 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 201 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 202 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 203 #define CONFIG_SYS_BAUDRATE_TABLE \ 204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 205 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 206 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 207 208 /* 209 * I2C 210 */ 211 #define CONFIG_SYS_I2C 212 #define CONFIG_SYS_I2C_FSL 213 #define CONFIG_SYS_FSL_I2C_SPEED 100000 214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 216 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 217 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 219 220 /* PEX8518 slave I2C interface */ 221 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 222 223 /* I2C DS1631 temperature sensor */ 224 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 225 226 /* I2C EEPROM - AT24C128B */ 227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 231 232 /* I2C RTC */ 233 #define CONFIG_RTC_M41T11 1 234 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 235 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 236 237 /* GPIO/EEPROM/SRAM */ 238 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 239 240 /* GPIO */ 241 #define CONFIG_PCA953X 242 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 243 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 244 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 245 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 246 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 247 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62 248 249 /* 250 * PU = pulled high, PD = pulled low 251 * I = input, O = output, IO = input/output 252 */ 253 /* PCA9557 @ 0x18*/ 254 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 255 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 256 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 257 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 258 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 259 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 260 261 /* PCA9557 @ 0x1c*/ 262 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 263 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ 264 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 265 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 266 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 267 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 268 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 269 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 270 271 /* PCA9557 @ 0x1e*/ 272 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 273 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 274 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 275 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 276 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 277 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ 278 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ 279 280 /* PCA9557 @ 0x1f */ 281 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ 282 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ 283 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ 284 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ 285 286 /* 287 * General PCI 288 * Memory space is mapped 1-1, but I/O space must start from 0. 289 */ 290 /* PCIE1 - PEX8518 */ 291 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 292 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 293 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 294 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 295 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 296 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 297 298 /* PCIE2 - VPX P1 */ 299 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 300 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 301 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 302 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 303 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 304 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 305 306 /* 307 * Networking options 308 */ 309 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 310 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 311 #define CONFIG_MII 1 /* MII PHY management */ 312 #define CONFIG_ETHPRIME "eTSEC1" 313 314 #define CONFIG_TSEC1 1 315 #define CONFIG_TSEC1_NAME "eTSEC1" 316 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 317 #define TSEC1_PHY_ADDR 1 318 #define TSEC1_PHYIDX 0 319 #define CONFIG_HAS_ETH0 320 321 #define CONFIG_TSEC2 1 322 #define CONFIG_TSEC2_NAME "eTSEC2" 323 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 324 #define TSEC2_PHY_ADDR 2 325 #define TSEC2_PHYIDX 0 326 #define CONFIG_HAS_ETH1 327 328 /* 329 * BAT mappings 330 */ 331 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 332 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 333 BATL_PP_RW |\ 334 BATL_CACHEINHIBIT |\ 335 BATL_GUARDEDSTORAGE) 336 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ 337 BATU_BL_1M |\ 338 BATU_VS |\ 339 BATU_VP) 340 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 341 BATL_PP_RW |\ 342 BATL_CACHEINHIBIT) 343 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 344 #endif 345 346 /* 347 * BAT0 2G Cacheable, non-guarded 348 * 0x0000_0000 2G DDR 349 */ 350 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 351 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 352 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 353 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 354 355 /* 356 * BAT1 1G Cache-inhibited, guarded 357 * 0x8000_0000 1G PCI-Express 1 Memory 358 */ 359 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 360 BATL_PP_RW |\ 361 BATL_CACHEINHIBIT |\ 362 BATL_GUARDEDSTORAGE) 363 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ 364 BATU_BL_1G |\ 365 BATU_VS |\ 366 BATU_VP) 367 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 368 BATL_PP_RW |\ 369 BATL_CACHEINHIBIT) 370 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 371 372 /* 373 * BAT2 512M Cache-inhibited, guarded 374 * 0xc000_0000 512M PCI-Express 2 Memory 375 */ 376 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 377 BATL_PP_RW |\ 378 BATL_CACHEINHIBIT |\ 379 BATL_GUARDEDSTORAGE) 380 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ 381 BATU_BL_512M |\ 382 BATU_VS |\ 383 BATU_VP) 384 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 385 BATL_PP_RW |\ 386 BATL_CACHEINHIBIT) 387 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 388 389 /* 390 * BAT3 1M Cache-inhibited, guarded 391 * 0xe000_0000 1M CCSR 392 */ 393 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ 394 BATL_PP_RW |\ 395 BATL_CACHEINHIBIT |\ 396 BATL_GUARDEDSTORAGE) 397 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ 398 BATU_BL_1M |\ 399 BATU_VS |\ 400 BATU_VP) 401 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ 402 BATL_PP_RW |\ 403 BATL_CACHEINHIBIT) 404 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 405 406 /* 407 * BAT4 32M Cache-inhibited, guarded 408 * 0xe200_0000 16M PCI-Express 1 I/O 409 * 0xe300_0000 16M PCI-Express 2 I/0 410 */ 411 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 412 BATL_PP_RW |\ 413 BATL_CACHEINHIBIT |\ 414 BATL_GUARDEDSTORAGE) 415 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ 416 BATU_BL_32M |\ 417 BATU_VS |\ 418 BATU_VP) 419 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 420 BATL_PP_RW |\ 421 BATL_CACHEINHIBIT) 422 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 423 424 /* 425 * BAT5 128K Cacheable, non-guarded 426 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) 427 */ 428 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ 429 BATL_PP_RW |\ 430 BATL_MEMCOHERENCE) 431 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ 432 BATU_BL_128K |\ 433 BATU_VS |\ 434 BATU_VP) 435 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 436 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 437 438 /* 439 * BAT6 256M Cache-inhibited, guarded 440 * 0xf000_0000 256M FLASH 441 */ 442 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ 443 BATL_PP_RW |\ 444 BATL_CACHEINHIBIT |\ 445 BATL_GUARDEDSTORAGE) 446 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ 447 BATU_BL_256M |\ 448 BATU_VS |\ 449 BATU_VP) 450 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ 451 BATL_PP_RW |\ 452 BATL_MEMCOHERENCE) 453 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 454 455 /* Map the last 1M of flash where we're running from reset */ 456 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 457 BATL_PP_RW |\ 458 BATL_CACHEINHIBIT |\ 459 BATL_GUARDEDSTORAGE) 460 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\ 461 BATU_BL_1M |\ 462 BATU_VS |\ 463 BATU_VP) 464 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 465 BATL_PP_RW |\ 466 BATL_MEMCOHERENCE) 467 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 468 469 /* 470 * BAT7 64M Cache-inhibited, guarded 471 * 0xe800_0000 64K NAND FLASH 472 * 0xe804_0000 128K DUART Registers 473 */ 474 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ 475 BATL_PP_RW |\ 476 BATL_CACHEINHIBIT |\ 477 BATL_GUARDEDSTORAGE) 478 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ 479 BATU_BL_512K |\ 480 BATU_VS |\ 481 BATU_VP) 482 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ 483 BATL_PP_RW |\ 484 BATL_CACHEINHIBIT) 485 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 486 487 /* 488 * Command configuration. 489 */ 490 #define CONFIG_CMD_EEPROM 491 #define CONFIG_CMD_IRQ 492 #define CONFIG_CMD_JFFS2 493 #define CONFIG_CMD_NAND 494 #define CONFIG_CMD_PCA953X 495 #define CONFIG_CMD_PCA953X_INFO 496 #define CONFIG_CMD_PCI 497 #define CONFIG_CMD_PCI_ENUM 498 #define CONFIG_CMD_REGINFO 499 500 /* 501 * Miscellaneous configurable options 502 */ 503 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 504 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 505 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 506 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 507 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 508 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 509 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ 510 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 511 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 512 #define CONFIG_PREBOOT /* enable preboot variable */ 513 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 514 515 /* 516 * For booting Linux, the board info and command line data 517 * have to be in the first 16 MB of memory, since this is 518 * the maximum mapped by the Linux kernel during initialization. 519 */ 520 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 521 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 522 523 /* 524 * Environment Configuration 525 */ 526 #define CONFIG_ENV_IS_IN_FLASH 1 527 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 528 #define CONFIG_ENV_SIZE 0x8000 529 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 530 531 /* 532 * Flash memory map: 533 * fffc0000 - ffffffff Pri FDT (256KB) 534 * fff80000 - fffbffff Pri U-Boot Environment (256 KB) 535 * fff00000 - fff7ffff Pri U-Boot (512 KB) 536 * fef00000 - ffefffff Pri OS image (16MB) 537 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 538 * 539 * f7fc0000 - f7ffffff Sec FDT (256KB) 540 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) 541 * f7f00000 - f7f7ffff Sec U-Boot (512 KB) 542 * f6f00000 - f7efffff Sec OS image (16MB) 543 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 544 */ 545 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000) 546 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000) 547 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000) 548 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000) 549 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 550 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 551 552 #define CONFIG_PROG_UBOOT1 \ 553 "$download_cmd $loadaddr $ubootfile; " \ 554 "if test $? -eq 0; then " \ 555 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 556 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 557 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 558 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 559 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 560 "if test $? -ne 0; then " \ 561 "echo PROGRAM FAILED; " \ 562 "else; " \ 563 "echo PROGRAM SUCCEEDED; " \ 564 "fi; " \ 565 "else; " \ 566 "echo DOWNLOAD FAILED; " \ 567 "fi;" 568 569 #define CONFIG_PROG_UBOOT2 \ 570 "$download_cmd $loadaddr $ubootfile; " \ 571 "if test $? -eq 0; then " \ 572 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 573 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 574 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 575 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 576 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 577 "if test $? -ne 0; then " \ 578 "echo PROGRAM FAILED; " \ 579 "else; " \ 580 "echo PROGRAM SUCCEEDED; " \ 581 "fi; " \ 582 "else; " \ 583 "echo DOWNLOAD FAILED; " \ 584 "fi;" 585 586 #define CONFIG_BOOT_OS_NET \ 587 "$download_cmd $osaddr $osfile; " \ 588 "if test $? -eq 0; then " \ 589 "if test -n $fdtaddr; then " \ 590 "$download_cmd $fdtaddr $fdtfile; " \ 591 "if test $? -eq 0; then " \ 592 "bootm $osaddr - $fdtaddr; " \ 593 "else; " \ 594 "echo FDT DOWNLOAD FAILED; " \ 595 "fi; " \ 596 "else; " \ 597 "bootm $osaddr; " \ 598 "fi; " \ 599 "else; " \ 600 "echo OS DOWNLOAD FAILED; " \ 601 "fi;" 602 603 #define CONFIG_PROG_OS1 \ 604 "$download_cmd $osaddr $osfile; " \ 605 "if test $? -eq 0; then " \ 606 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 607 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 608 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 609 "if test $? -ne 0; then " \ 610 "echo OS PROGRAM FAILED; " \ 611 "else; " \ 612 "echo OS PROGRAM SUCCEEDED; " \ 613 "fi; " \ 614 "else; " \ 615 "echo OS DOWNLOAD FAILED; " \ 616 "fi;" 617 618 #define CONFIG_PROG_OS2 \ 619 "$download_cmd $osaddr $osfile; " \ 620 "if test $? -eq 0; then " \ 621 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 622 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 623 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 624 "if test $? -ne 0; then " \ 625 "echo OS PROGRAM FAILED; " \ 626 "else; " \ 627 "echo OS PROGRAM SUCCEEDED; " \ 628 "fi; " \ 629 "else; " \ 630 "echo OS DOWNLOAD FAILED; " \ 631 "fi;" 632 633 #define CONFIG_PROG_FDT1 \ 634 "$download_cmd $fdtaddr $fdtfile; " \ 635 "if test $? -eq 0; then " \ 636 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 637 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 638 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 639 "if test $? -ne 0; then " \ 640 "echo FDT PROGRAM FAILED; " \ 641 "else; " \ 642 "echo FDT PROGRAM SUCCEEDED; " \ 643 "fi; " \ 644 "else; " \ 645 "echo FDT DOWNLOAD FAILED; " \ 646 "fi;" 647 648 #define CONFIG_PROG_FDT2 \ 649 "$download_cmd $fdtaddr $fdtfile; " \ 650 "if test $? -eq 0; then " \ 651 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 652 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 653 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 654 "if test $? -ne 0; then " \ 655 "echo FDT PROGRAM FAILED; " \ 656 "else; " \ 657 "echo FDT PROGRAM SUCCEEDED; " \ 658 "fi; " \ 659 "else; " \ 660 "echo FDT DOWNLOAD FAILED; " \ 661 "fi;" 662 663 #define CONFIG_EXTRA_ENV_SETTINGS \ 664 "autoload=yes\0" \ 665 "download_cmd=tftp\0" \ 666 "console_args=console=ttyS0,115200\0" \ 667 "root_args=root=/dev/nfs rw\0" \ 668 "misc_args=ip=on\0" \ 669 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 670 "bootfile=/home/user/file\0" \ 671 "osfile=/home/user/board.uImage\0" \ 672 "fdtfile=/home/user/board.dtb\0" \ 673 "ubootfile=/home/user/u-boot.bin\0" \ 674 "fdtaddr=0x1e00000\0" \ 675 "osaddr=0x1000000\0" \ 676 "loadaddr=0x1000000\0" \ 677 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 678 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 679 "prog_os1="CONFIG_PROG_OS1"\0" \ 680 "prog_os2="CONFIG_PROG_OS2"\0" \ 681 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 682 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 683 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 684 "bootcmd_flash1=run set_bootargs; " \ 685 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 686 "bootcmd_flash2=run set_bootargs; " \ 687 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 688 "bootcmd=run bootcmd_flash1\0" 689 #endif /* __CONFIG_H */ 690