1 /* 2 * Configuration for Xilinx ZynqMP zcu102 3 * 4 * (C) Copyright 2015 Xilinx, Inc. 5 * Michal Simek <michal.simek@xilinx.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_ZYNQMP_ZCU102_H 11 #define __CONFIG_ZYNQMP_ZCU102_H 12 13 #define CONFIG_ZYNQ_SDHCI1 14 #define CONFIG_ZYNQ_I2C0 15 #define CONFIG_ZYNQ_I2C1 16 #define CONFIG_SYS_I2C_MAX_HOPS 1 17 #define CONFIG_SYS_NUM_I2C_BUSES 18 18 #define CONFIG_SYS_I2C_BUSES { \ 19 {0, {I2C_NULL_HOP} }, \ 20 {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ 21 {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ 22 {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ 23 {1, {I2C_NULL_HOP} }, \ 24 {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ 25 {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ 26 {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ 27 {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ 28 {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ 29 {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ 30 {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ 31 {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ 32 {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ 33 {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ 34 {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ 35 {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ 36 {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ 37 } 38 39 #define CONFIG_SYS_I2C_ZYNQ 40 #define CONFIG_PCA953X 41 #define CONFIG_CMD_PCA953X 42 #define CONFIG_CMD_PCA953X_INFO 43 44 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} 45 46 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 47 #define CONFIG_CMD_EEPROM 48 #define CONFIG_ZYNQ_EEPROM_BUS 5 49 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 50 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 51 52 #include <configs/xilinx_zynqmp.h> 53 54 #endif /* __CONFIG_ZYNQMP_ZCU102_H */ 55