11f4f3d33SMichal Simek /* 21f4f3d33SMichal Simek * Configuration for Xilinx ZynqMP zcu102 31f4f3d33SMichal Simek * 41f4f3d33SMichal Simek * (C) Copyright 2015 Xilinx, Inc. 51f4f3d33SMichal Simek * Michal Simek <michal.simek@xilinx.com> 61f4f3d33SMichal Simek * 71f4f3d33SMichal Simek * SPDX-License-Identifier: GPL-2.0+ 81f4f3d33SMichal Simek */ 91f4f3d33SMichal Simek 101f4f3d33SMichal Simek #ifndef __CONFIG_ZYNQMP_ZCU102_H 111f4f3d33SMichal Simek #define __CONFIG_ZYNQMP_ZCU102_H 121f4f3d33SMichal Simek 131f4f3d33SMichal Simek #define CONFIG_ZYNQ_SDHCI1 141f4f3d33SMichal Simek #define CONFIG_ZYNQ_I2C0 151f4f3d33SMichal Simek #define CONFIG_ZYNQ_I2C1 161f4f3d33SMichal Simek #define CONFIG_SYS_I2C_MAX_HOPS 1 171f4f3d33SMichal Simek #define CONFIG_SYS_NUM_I2C_BUSES 18 181f4f3d33SMichal Simek #define CONFIG_SYS_I2C_BUSES { \ 191f4f3d33SMichal Simek {0, {I2C_NULL_HOP} }, \ 201f4f3d33SMichal Simek {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ 211f4f3d33SMichal Simek {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ 221f4f3d33SMichal Simek {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ 231f4f3d33SMichal Simek {1, {I2C_NULL_HOP} }, \ 241f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ 251f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ 261f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ 271f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ 281f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ 291f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ 301f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ 311f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ 321f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ 331f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ 341f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ 351f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ 361f4f3d33SMichal Simek {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ 371f4f3d33SMichal Simek } 381f4f3d33SMichal Simek 391f4f3d33SMichal Simek #define CONFIG_SYS_I2C_ZYNQ 40ff9bd8e9SMichal Simek #define CONFIG_PCA953X 41ff9bd8e9SMichal Simek 421f4f3d33SMichal Simek #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} 431f4f3d33SMichal Simek 44*6919b4bfSMichal Simek #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 45*6919b4bfSMichal Simek #define CONFIG_ZYNQ_EEPROM_BUS 5 46*6919b4bfSMichal Simek #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 47*6919b4bfSMichal Simek #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 48*6919b4bfSMichal Simek 491f4f3d33SMichal Simek #include <configs/xilinx_zynqmp.h> 501f4f3d33SMichal Simek 511f4f3d33SMichal Simek #endif /* __CONFIG_ZYNQMP_ZCU102_H */ 52