1 /* 2 * Configuration for Xilinx ZynqMP zc1751 XM015 DC1 3 * 4 * (C) Copyright 2015 Xilinx, Inc. 5 * Michal Simek <michal.simek@xilinx.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H 11 #define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H 12 13 #define CONFIG_ZYNQ_SDHCI0 14 #define CONFIG_ZYNQ_SDHCI1 15 #define CONFIG_AHCI 16 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} 17 18 #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1" 19 20 #define CONFIG_KERNEL_FDT_OFST_SIZE \ 21 "kernel_offset=0x400000\0" \ 22 "fdt_offset=0x2400000\0" \ 23 "kernel_size=0x2000000\0" \ 24 "fdt_size=0x80000\0" \ 25 "board=zc1751-dc1\0" 26 27 #include <configs/xilinx_zynqmp.h> 28 29 #endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ 30