1 /* 2 * Configuration for Xilinx ZynqMP emulation platforms 3 * 4 * (C) Copyright 2014 - 2015 Xilinx, Inc. 5 * Michal Simek <michal.simek@xilinx.com> 6 * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 7 * 8 * Based on Configuration for Versatile Express 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_ZYNQMP_EP_H 14 #define __CONFIG_ZYNQMP_EP_H 15 16 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 17 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) 18 #define CONFIG_ZYNQ_EEPROM 19 #define CONFIG_AHCI 20 #define CONFIG_SATA_CEVA 21 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ 22 ZYNQMP_USB1_XHCI_BASEADDR} 23 24 #define COUNTER_FREQUENCY 4000000 25 26 #include <configs/xilinx_zynqmp.h> 27 28 #endif /* __CONFIG_ZYNQMP_EP_H */ 29