10b54a9ddSSiva Durga Prasad Paladugu /* 20b54a9ddSSiva Durga Prasad Paladugu * Configuration for Xilinx ZynqMP emulation 30b54a9ddSSiva Durga Prasad Paladugu * platforms. See zynqmp-common.h for ZynqMP 40b54a9ddSSiva Durga Prasad Paladugu * common configs 50b54a9ddSSiva Durga Prasad Paladugu * 60b54a9ddSSiva Durga Prasad Paladugu * (C) Copyright 2014 - 2015 Xilinx, Inc. 70b54a9ddSSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 80b54a9ddSSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 90b54a9ddSSiva Durga Prasad Paladugu * 100b54a9ddSSiva Durga Prasad Paladugu * Based on Configuration for Versatile Express 110b54a9ddSSiva Durga Prasad Paladugu * 120b54a9ddSSiva Durga Prasad Paladugu * SPDX-License-Identifier: GPL-2.0+ 130b54a9ddSSiva Durga Prasad Paladugu */ 140b54a9ddSSiva Durga Prasad Paladugu 150b54a9ddSSiva Durga Prasad Paladugu #ifndef __CONFIG_ZYNQMP_EP_H 160b54a9ddSSiva Durga Prasad Paladugu #define __CONFIG_ZYNQMP_EP_H 170b54a9ddSSiva Durga Prasad Paladugu 180b54a9ddSSiva Durga Prasad Paladugu #define CONFIG_ZYNQ_SDHCI0 19f3bd7280SMichal Simek #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 20*c061d5b3SSiva Durga Prasad Paladugu #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) 210b54a9ddSSiva Durga Prasad Paladugu #define CONFIG_ZYNQ_I2C0 220b54a9ddSSiva Durga Prasad Paladugu #define CONFIG_SYS_I2C_ZYNQ 230b54a9ddSSiva Durga Prasad Paladugu #define CONFIG_ZYNQ_EEPROM 246fe6f135SMichal Simek #define CONFIG_AHCI 25f4dd69caSSiva Durga Prasad Paladugu #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ 26f4dd69caSSiva Durga Prasad Paladugu ZYNQMP_USB1_XHCI_BASEADDR} 270b54a9ddSSiva Durga Prasad Paladugu 280b54a9ddSSiva Durga Prasad Paladugu #include <configs/xilinx_zynqmp.h> 290b54a9ddSSiva Durga Prasad Paladugu 300b54a9ddSSiva Durga Prasad Paladugu #endif /* __CONFIG_ZYNQMP_EP_H */ 31