10b54a9ddSSiva Durga Prasad Paladugu /* 2d041e3e1SMichal Simek * Configuration for Xilinx ZynqMP emulation platforms 30b54a9ddSSiva Durga Prasad Paladugu * 40b54a9ddSSiva Durga Prasad Paladugu * (C) Copyright 2014 - 2015 Xilinx, Inc. 50b54a9ddSSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 60b54a9ddSSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 70b54a9ddSSiva Durga Prasad Paladugu * 80b54a9ddSSiva Durga Prasad Paladugu * Based on Configuration for Versatile Express 90b54a9ddSSiva Durga Prasad Paladugu * 100b54a9ddSSiva Durga Prasad Paladugu * SPDX-License-Identifier: GPL-2.0+ 110b54a9ddSSiva Durga Prasad Paladugu */ 120b54a9ddSSiva Durga Prasad Paladugu 130b54a9ddSSiva Durga Prasad Paladugu #ifndef __CONFIG_ZYNQMP_EP_H 140b54a9ddSSiva Durga Prasad Paladugu #define __CONFIG_ZYNQMP_EP_H 150b54a9ddSSiva Durga Prasad Paladugu 16f3bd7280SMichal Simek #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 17*913a6eebSSiva Durga Prasad Paladugu #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9) 180b54a9ddSSiva Durga Prasad Paladugu #define CONFIG_ZYNQ_EEPROM 19f4dd69caSSiva Durga Prasad Paladugu #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ 20f4dd69caSSiva Durga Prasad Paladugu ZYNQMP_USB1_XHCI_BASEADDR} 210b54a9ddSSiva Durga Prasad Paladugu 22713b6164SMichal Simek #define COUNTER_FREQUENCY 4000000 23713b6164SMichal Simek 240b54a9ddSSiva Durga Prasad Paladugu #include <configs/xilinx_zynqmp.h> 250b54a9ddSSiva Durga Prasad Paladugu 260b54a9ddSSiva Durga Prasad Paladugu #endif /* __CONFIG_ZYNQMP_EP_H */ 27