1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 20 #include <asm/arch/hardware.h> 21 22 /* Timer, HZ specific defines */ 23 #define CONFIG_SYS_HZ_CLOCK 8300000 24 25 #define CONFIG_SYS_TEXT_BASE 0x00800040 26 #define CONFIG_SYS_FLASH_BASE 0xf8000000 27 /* Reserve 8KiB for SPL */ 28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 31 CONFIG_SYS_SPL_LEN) 32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 34 #define CONFIG_SYS_MONITOR_LEN 0x60000 35 36 /* Serial Configuration (PL011) */ 37 #define CONFIG_SYS_SERIAL0 0xD0000000 38 #define CONFIG_SYS_SERIAL1 0xD0080000 39 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 40 (void *)CONFIG_SYS_SERIAL1 } 41 #define CONFIG_PL011_SERIAL 42 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 43 #define CONFIG_CONS_INDEX 0 44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 45 57600, 115200 } 46 #define CONFIG_SYS_LOADS_BAUD_CHANGE 47 48 /* NOR FLASH config options */ 49 #define CONFIG_ST_SMI 50 #define CONFIG_SYS_MAX_FLASH_BANKS 1 51 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 52 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 53 #define CONFIG_SYS_MAX_FLASH_SECT 128 54 #define CONFIG_SYS_FLASH_EMPTY_INFO 55 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 56 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 57 58 /* NAND FLASH config options */ 59 #define CONFIG_NAND_FSMC 60 #define CONFIG_SYS_NAND_SELF_INIT 61 #define CONFIG_SYS_MAX_NAND_DEVICE 1 62 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 63 #define CONFIG_MTD_ECC_SOFT 64 #define CONFIG_SYS_FSMC_NAND_8BIT 65 #define CONFIG_SYS_NAND_ONFI_DETECTION 66 #define CONFIG_NAND_ECC_BCH 67 68 /* UBI/UBI config options */ 69 #define CONFIG_MTD_DEVICE 70 #define CONFIG_MTD_PARTITIONS 71 72 /* Ethernet config options */ 73 #define CONFIG_MII 74 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 75 #define CONFIG_PHY_ADDR 0 /* PHY address */ 76 77 #define CONFIG_SPEAR_GPIO 78 79 /* I2C config options */ 80 #define CONFIG_SYS_I2C 81 #define CONFIG_SYS_I2C_BASE 0xD0200000 82 #define CONFIG_SYS_I2C_SPEED 400000 83 #define CONFIG_SYS_I2C_SLAVE 0x02 84 #define CONFIG_I2C_CHIPADDRESS 0x50 85 86 #define CONFIG_RTC_M41T62 1 87 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 88 89 /* FPGA config options */ 90 #define CONFIG_FPGA 91 #define CONFIG_FPGA_XILINX 92 #define CONFIG_FPGA_SPARTAN3 93 #define CONFIG_FPGA_COUNT 1 94 95 /* USB EHCI options */ 96 #define CONFIG_USB_EHCI_SPEAR 97 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 98 99 /* Filesystem support (for USB key) */ 100 #define CONFIG_SUPPORT_VFAT 101 102 103 /* 104 * U-Boot Environment placing definitions. 105 */ 106 #define CONFIG_ENV_SECT_SIZE 0x00010000 107 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 108 CONFIG_SYS_MONITOR_LEN) 109 #define CONFIG_ENV_SIZE 0x02000 110 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 111 CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 113 114 /* Miscellaneous configurable options */ 115 #define CONFIG_ARCH_CPU_INIT 116 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 117 #define CONFIG_CMDLINE_TAG 118 #define CONFIG_SETUP_MEMORY_TAGS 119 #define CONFIG_MISC_INIT_R 120 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 121 122 #define CONFIG_SYS_MEMTEST_START 0x00800000 123 #define CONFIG_SYS_MEMTEST_END 0x04000000 124 #define CONFIG_SYS_MALLOC_LEN (8 << 20) 125 #define CONFIG_SYS_LONGHELP 126 #define CONFIG_CMDLINE_EDITING 127 #define CONFIG_AUTO_COMPLETE 128 #define CONFIG_SYS_MAXARGS 16 129 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 130 #define CONFIG_SYS_LOAD_ADDR 0x00800000 131 132 /* Use last 2 lwords in internal SRAM for bootcounter */ 133 #define CONFIG_BOOTCOUNT_LIMIT 134 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ 135 CONFIG_SRAM_SIZE) 136 137 #define CONFIG_HOSTNAME x600 138 #define CONFIG_UBI_PART ubi0 139 #define CONFIG_UBIFS_VOLUME rootfs 140 141 #define MTDIDS_DEFAULT "nand0=nand" 142 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 143 144 #define CONFIG_EXTRA_ENV_SETTINGS \ 145 "u-boot_addr=1000000\0" \ 146 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 147 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 148 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 149 " +${filesize};" \ 150 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 151 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 152 " ${filesize};" \ 153 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 154 " +${filesize}\0" \ 155 "upd=run load update\0" \ 156 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ 157 "part=" __stringify(CONFIG_UBI_PART) "\0" \ 158 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 159 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 160 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 161 " ${filesize}\0" \ 162 "upd_ubifs=run load_ubifs update_ubifs\0" \ 163 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 164 "ubi create ${vol} 4000000\0" \ 165 "netdev=eth0\0" \ 166 "rootpath=/opt/eldk-4.2/arm\0" \ 167 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 168 "nfsroot=${serverip}:${rootpath}\0" \ 169 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 170 "boot_part=0\0" \ 171 "altbootcmd=if test $boot_part -eq 0;then " \ 172 "echo Switching to partition 1!;" \ 173 "setenv boot_part 1;" \ 174 "else; " \ 175 "echo Switching to partition 0!;" \ 176 "setenv boot_part 0;" \ 177 "fi;" \ 178 "saveenv;boot\0" \ 179 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 180 "root=ubi0:rootfs rootfstype=ubifs\0" \ 181 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 182 "kernel_fs=/boot/uImage \0" \ 183 "kernel_addr=1000000\0" \ 184 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ 185 __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 186 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 187 "dtb_addr=1800000\0" \ 188 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 189 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 190 "addip=setenv bootargs ${bootargs} " \ 191 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 192 ":${hostname}:${netdev}:off panic=1\0" \ 193 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 194 "${baudrate}\0" \ 195 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 196 "net_nfs=run load_dtb load_kernel; " \ 197 "run nfsargs addip addcon addmtd addmisc;" \ 198 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 199 "mtdids=" MTDIDS_DEFAULT "\0" \ 200 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 201 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 202 " addcon addmisc addmtd;" \ 203 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 204 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 205 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 206 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 207 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 208 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 209 "bootcmd=run nand_ubifs\0" \ 210 "\0" 211 212 /* Physical Memory Map */ 213 #define CONFIG_NR_DRAM_BANKS 1 214 #define PHYS_SDRAM_1 0x00000000 215 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 216 217 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 218 #define CONFIG_SRAM_BASE 0xd2800000 219 /* Preserve the last 2 lwords for the boot-counter */ 220 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) 221 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE 222 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE 223 224 #define CONFIG_SYS_INIT_SP_OFFSET \ 225 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 226 227 #define CONFIG_SYS_INIT_SP_ADDR \ 228 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 229 230 /* 231 * SPL related defines 232 */ 233 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 234 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) 235 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 236 237 #define CONFIG_SPL_FRAMEWORK 238 239 /* 240 * Please select/define only one of the following 241 * Each definition corresponds to a supported DDR chip. 242 * DDR configuration is based on the following selection 243 */ 244 #define CONFIG_DDR_MT47H64M16 1 245 #define CONFIG_DDR_MT47H32M16 0 246 #define CONFIG_DDR_MT47H128M8 0 247 248 /* 249 * Synchronous/Asynchronous operation of DDR 250 * 251 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 252 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 253 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 254 */ 255 #define CONFIG_DDR_2HCLK 1 256 #define CONFIG_DDR_HCLK 0 257 #define CONFIG_DDR_PLL2 0 258 259 /* 260 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 261 * or not. Modify/Add to only these macros to define new boot types 262 */ 263 #define USB_BOOT_SUPPORTED 0 264 #define PCIE_BOOT_SUPPORTED 0 265 #define SNOR_BOOT_SUPPORTED 1 266 #define NAND_BOOT_SUPPORTED 1 267 #define PNOR_BOOT_SUPPORTED 0 268 #define TFTP_BOOT_SUPPORTED 0 269 #define UART_BOOT_SUPPORTED 0 270 #define SPI_BOOT_SUPPORTED 0 271 #define I2C_BOOT_SUPPORTED 0 272 #define MMC_BOOT_SUPPORTED 0 273 274 #endif /* __CONFIG_H */ 275