1d81b27a2SStefano Babic /* 2d81b27a2SStefano Babic * (C) Copyright 2011, Stefano Babic <sbabic@denx.de> 3d81b27a2SStefano Babic * 4d81b27a2SStefano Babic * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5d81b27a2SStefano Babic * 6d81b27a2SStefano Babic * Configuration for the woodburn board. 7d81b27a2SStefano Babic * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9d81b27a2SStefano Babic */ 10d81b27a2SStefano Babic 11d81b27a2SStefano Babic #ifndef __WOODBURN_COMMON_CONFIG_H 12d81b27a2SStefano Babic #define __WOODBURN_COMMON_CONFIG_H 13d81b27a2SStefano Babic 14d81b27a2SStefano Babic #include <asm/arch/imx-regs.h> 15d81b27a2SStefano Babic 16d81b27a2SStefano Babic /* High Level Configuration Options */ 17d81b27a2SStefano Babic #define CONFIG_MX35 18d81b27a2SStefano Babic #define CONFIG_MX35_HCLK_FREQ 24000000 19*18fb0e3cSGong Qianyu #define CONFIG_SYS_FSL_CLK 20d81b27a2SStefano Babic 21d81b27a2SStefano Babic #define CONFIG_SYS_DCACHE_OFF 22d81b27a2SStefano Babic 23d81b27a2SStefano Babic #define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 24d81b27a2SStefano Babic 25d81b27a2SStefano Babic /* This is required to setup the ESDC controller */ 26d81b27a2SStefano Babic 27d81b27a2SStefano Babic #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 28d81b27a2SStefano Babic #define CONFIG_REVISION_TAG 29d81b27a2SStefano Babic #define CONFIG_SETUP_MEMORY_TAGS 30d81b27a2SStefano Babic #define CONFIG_INITRD_TAG 31d81b27a2SStefano Babic 32d81b27a2SStefano Babic /* 33d81b27a2SStefano Babic * Size of malloc() pool 34d81b27a2SStefano Babic */ 35d81b27a2SStefano Babic #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 36d81b27a2SStefano Babic 37d81b27a2SStefano Babic /* 38d81b27a2SStefano Babic * Hardware drivers 39d81b27a2SStefano Babic */ 40b089d039Strem #define CONFIG_SYS_I2C 41b089d039Strem #define CONFIG_SYS_I2C_MXC 4203544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 4303544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 44f8cb101eSYork Sun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 45b089d039Strem #define CONFIG_SYS_SPD_BUS_NUM 0 46d81b27a2SStefano Babic #define CONFIG_MXC_SPI 47d81b27a2SStefano Babic #define CONFIG_MXC_GPIO 48d81b27a2SStefano Babic 49d81b27a2SStefano Babic /* PMIC Controller */ 5005a860c2SStefano Babic #define CONFIG_POWER 5105a860c2SStefano Babic #define CONFIG_POWER_I2C 5205a860c2SStefano Babic #define CONFIG_POWER_FSL 53913702caSSimon Glass #define CONFIG_POWER_FSL_MC13892 54d81b27a2SStefano Babic #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 55d81b27a2SStefano Babic #define CONFIG_RTC_MC13XXX 56d81b27a2SStefano Babic 57d81b27a2SStefano Babic /* mmc driver */ 58d81b27a2SStefano Babic #define CONFIG_FSL_ESDHC 59d81b27a2SStefano Babic #define CONFIG_SYS_FSL_ESDHC_ADDR 0 60d81b27a2SStefano Babic #define CONFIG_SYS_FSL_ESDHC_NUM 1 61d81b27a2SStefano Babic 62d81b27a2SStefano Babic /* 63d81b27a2SStefano Babic * UART (console) 64d81b27a2SStefano Babic */ 65d81b27a2SStefano Babic #define CONFIG_MXC_UART 66d81b27a2SStefano Babic #define CONFIG_MXC_UART_BASE UART1_BASE 67d81b27a2SStefano Babic 68d81b27a2SStefano Babic /* allow to overwrite serial and ethaddr */ 69d81b27a2SStefano Babic #define CONFIG_ENV_OVERWRITE 70d81b27a2SStefano Babic #define CONFIG_CONS_INDEX 1 71d81b27a2SStefano Babic 72d81b27a2SStefano Babic /* 73d81b27a2SStefano Babic * Command definition 74d81b27a2SStefano Babic */ 75d81b27a2SStefano Babic #define CONFIG_BOOTP_SUBNETMASK 76d81b27a2SStefano Babic #define CONFIG_BOOTP_GATEWAY 77d81b27a2SStefano Babic #define CONFIG_BOOTP_DNS 78d81b27a2SStefano Babic 79d81b27a2SStefano Babic #define CONFIG_MXC_GPIO 80d81b27a2SStefano Babic 81d81b27a2SStefano Babic #define CONFIG_NET_RETRY_COUNT 100 82d81b27a2SStefano Babic 83d81b27a2SStefano Babic 84d81b27a2SStefano Babic #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 85d81b27a2SStefano Babic 86d81b27a2SStefano Babic /* 87d81b27a2SStefano Babic * Ethernet on SOC (FEC) 88d81b27a2SStefano Babic */ 89d81b27a2SStefano Babic #define CONFIG_FEC_MXC 90d81b27a2SStefano Babic #define IMX_FEC_BASE FEC_BASE_ADDR 91d81b27a2SStefano Babic #define CONFIG_FEC_MXC_PHYADDR 0x1 92d81b27a2SStefano Babic 93d81b27a2SStefano Babic #define CONFIG_MII 94d81b27a2SStefano Babic #define CONFIG_DISCOVER_PHY 95d81b27a2SStefano Babic 96d81b27a2SStefano Babic #define CONFIG_ARP_TIMEOUT 200UL 97d81b27a2SStefano Babic 98d81b27a2SStefano Babic /* 99d81b27a2SStefano Babic * Miscellaneous configurable options 100d81b27a2SStefano Babic */ 101d81b27a2SStefano Babic #define CONFIG_SYS_LONGHELP /* undef to save memory */ 102d81b27a2SStefano Babic #define CONFIG_CMDLINE_EDITING 103d81b27a2SStefano Babic 104d81b27a2SStefano Babic #define CONFIG_AUTO_COMPLETE 105d81b27a2SStefano Babic 106d81b27a2SStefano Babic #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 107d81b27a2SStefano Babic #define CONFIG_SYS_MEMTEST_END 0x10000 108d81b27a2SStefano Babic 109d81b27a2SStefano Babic #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 110d81b27a2SStefano Babic 111d81b27a2SStefano Babic /* 112d81b27a2SStefano Babic * Physical Memory Map 113d81b27a2SStefano Babic */ 114d81b27a2SStefano Babic #define CONFIG_NR_DRAM_BANKS 1 115d81b27a2SStefano Babic #define PHYS_SDRAM_1 CSD0_BASE_ADDR 116d81b27a2SStefano Babic #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) 117d81b27a2SStefano Babic 118d81b27a2SStefano Babic #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR 119d81b27a2SStefano Babic 120d81b27a2SStefano Babic #define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \ 121d81b27a2SStefano Babic IRAM_BASE_ADDR - \ 122d81b27a2SStefano Babic GENERATED_GBL_DATA_SIZE) 123d81b27a2SStefano Babic #define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \ 124d81b27a2SStefano Babic CONFIG_SYS_GBL_DATA_OFFSET) 125d81b27a2SStefano Babic 126d81b27a2SStefano Babic /* 127d81b27a2SStefano Babic * MTD Command for mtdparts 128d81b27a2SStefano Babic */ 129d81b27a2SStefano Babic #define CONFIG_FLASH_CFI_MTD 130d81b27a2SStefano Babic 131d81b27a2SStefano Babic /* 132d81b27a2SStefano Babic * FLASH and environment organization 133d81b27a2SStefano Babic */ 134d81b27a2SStefano Babic #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR 135d81b27a2SStefano Babic #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 136d81b27a2SStefano Babic #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 137d81b27a2SStefano Babic /* Monitor at beginning of flash */ 138d81b27a2SStefano Babic #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 139d81b27a2SStefano Babic #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 140d81b27a2SStefano Babic 141d81b27a2SStefano Babic #define CONFIG_ENV_SECT_SIZE (128 * 1024) 142d81b27a2SStefano Babic #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 143d81b27a2SStefano Babic 144d81b27a2SStefano Babic /* Address and size of Redundant Environment Sector */ 145d81b27a2SStefano Babic #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 146d81b27a2SStefano Babic #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 147d81b27a2SStefano Babic 148d81b27a2SStefano Babic #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 149d81b27a2SStefano Babic CONFIG_SYS_MONITOR_LEN) 150d81b27a2SStefano Babic 151d81b27a2SStefano Babic /* 152d81b27a2SStefano Babic * CFI FLASH driver setup 153d81b27a2SStefano Babic */ 154d81b27a2SStefano Babic #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 155d81b27a2SStefano Babic #define CONFIG_FLASH_CFI_DRIVER 156d81b27a2SStefano Babic 157d81b27a2SStefano Babic /* A non-standard buffered write algorithm */ 158d81b27a2SStefano Babic #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ 159d81b27a2SStefano Babic #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ 160d81b27a2SStefano Babic 161d81b27a2SStefano Babic /* 162d81b27a2SStefano Babic * NAND FLASH driver setup 163d81b27a2SStefano Babic */ 164d81b27a2SStefano Babic #define CONFIG_NAND_MXC_V1_1 165d81b27a2SStefano Babic #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) 166d81b27a2SStefano Babic #define CONFIG_SYS_MAX_NAND_DEVICE 1 167d81b27a2SStefano Babic #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) 168d81b27a2SStefano Babic #define CONFIG_MXC_NAND_HWECC 169d81b27a2SStefano Babic #define CONFIG_SYS_NAND_LARGEPAGE 170d81b27a2SStefano Babic 171d81b27a2SStefano Babic #define CONFIG_SYS_NAND_ONFI_DETECTION 172d81b27a2SStefano Babic 173d81b27a2SStefano Babic /* 174d81b27a2SStefano Babic * Default environment and default scripts 175d81b27a2SStefano Babic * to update uboot and load kernel 176d81b27a2SStefano Babic */ 177d81b27a2SStefano Babic 178d81b27a2SStefano Babic #define CONFIG_HOSTNAME woodburn 179d81b27a2SStefano Babic #define CONFIG_EXTRA_ENV_SETTINGS \ 180d81b27a2SStefano Babic "netdev=eth0\0" \ 181d81b27a2SStefano Babic "nfsargs=setenv bootargs root=/dev/nfs rw " \ 182d81b27a2SStefano Babic "nfsroot=${serverip}:${rootpath}\0" \ 183d81b27a2SStefano Babic "ramargs=setenv bootargs root=/dev/ram rw\0" \ 184d81b27a2SStefano Babic "addip_sta=setenv bootargs ${bootargs} " \ 185d81b27a2SStefano Babic "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 186d81b27a2SStefano Babic ":${hostname}:${netdev}:off panic=1\0" \ 187d81b27a2SStefano Babic "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 188d81b27a2SStefano Babic "addip=if test -n ${ipdyn};then run addip_dyn;" \ 189d81b27a2SStefano Babic "else run addip_sta;fi\0" \ 190d81b27a2SStefano Babic "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 191d81b27a2SStefano Babic "addtty=setenv bootargs ${bootargs}" \ 192d81b27a2SStefano Babic " console=ttymxc0,${baudrate}\0" \ 193d81b27a2SStefano Babic "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 194d81b27a2SStefano Babic "loadaddr=80800000\0" \ 195d81b27a2SStefano Babic "kernel_addr_r=80800000\0" \ 1964a8c3f69SAnatolij Gustschin "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 1974a8c3f69SAnatolij Gustschin "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 1984a8c3f69SAnatolij Gustschin "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ 199d81b27a2SStefano Babic "flash_self=run ramargs addip addtty addmtd addmisc;" \ 200d81b27a2SStefano Babic "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 201d81b27a2SStefano Babic "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 202d81b27a2SStefano Babic "bootm ${kernel_addr}\0" \ 203d81b27a2SStefano Babic "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 204d81b27a2SStefano Babic "run nfsargs addip addtty addmtd addmisc;" \ 205d81b27a2SStefano Babic "bootm ${kernel_addr_r}\0" \ 206d81b27a2SStefano Babic "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ 207d81b27a2SStefano Babic "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ 208d81b27a2SStefano Babic "net_self=if run net_self_load;then " \ 209d81b27a2SStefano Babic "run ramargs addip addtty addmtd addmisc;" \ 210d81b27a2SStefano Babic "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 211d81b27a2SStefano Babic "else echo Images not loades;fi\0" \ 2124a8c3f69SAnatolij Gustschin "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ 213d81b27a2SStefano Babic "load=tftp ${loadaddr} ${u-boot}\0" \ 2144a8c3f69SAnatolij Gustschin "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 215d81b27a2SStefano Babic "update=protect off ${uboot_addr} +80000;" \ 216d81b27a2SStefano Babic "erase ${uboot_addr} +80000;" \ 217d81b27a2SStefano Babic "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ 218d81b27a2SStefano Babic "upd=if run load;then echo Updating u-boot;if run update;" \ 219d81b27a2SStefano Babic "then echo U-Boot updated;" \ 220d81b27a2SStefano Babic "else echo Error updating u-boot !;" \ 221d81b27a2SStefano Babic "echo Board without bootloader !!;" \ 222d81b27a2SStefano Babic "fi;" \ 223d81b27a2SStefano Babic "else echo U-Boot not downloaded..exiting;fi\0" \ 224d81b27a2SStefano Babic "bootcmd=run net_nfs\0" 225d81b27a2SStefano Babic 226d81b27a2SStefano Babic #endif /* __CONFIG_H */ 227