1 /* 2 * esd vme8349 U-Boot configuration file 3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4 * 5 * (C) Copyright 2006-2010 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * reinhard.arlt@esd-electronics.de 9 * Based on the MPC8349EMDS config. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 /* 31 * vme8349 board configuration file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* 38 * Top level Makefile configuration choices 39 */ 40 #ifdef CONFIG_CADDY2 41 #define VME_CADDY2 42 #endif 43 44 /* 45 * High Level Configuration Options 46 */ 47 #define CONFIG_E300 1 /* E300 Family */ 48 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 49 #define CONFIG_MPC834x 1 /* MPC834x family */ 50 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 51 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 52 53 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 54 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_PCI 58 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 59 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 60 61 #define CONFIG_PCI_66M 62 #ifdef CONFIG_PCI_66M 63 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 64 #else 65 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 66 #endif 67 68 #ifndef CONFIG_SYS_CLK_FREQ 69 #ifdef CONFIG_PCI_66M 70 #define CONFIG_SYS_CLK_FREQ 66000000 71 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 72 #else 73 #define CONFIG_SYS_CLK_FREQ 33000000 74 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 75 #endif 76 #endif 77 78 #define CONFIG_SYS_IMMR 0xE0000000 79 80 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 81 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 82 #define CONFIG_SYS_MEMTEST_END 0x00100000 83 84 /* 85 * DDR Setup 86 */ 87 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 88 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 89 #define CONFIG_SPD_EEPROM 90 #define SPD_EEPROM_ADDRESS 0x54 91 #define CONFIG_SYS_READ_SPD vme8349_read_spd 92 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 93 94 /* 95 * 32-bit data path mode. 96 * 97 * Please note that using this mode for devices with the real density of 64-bit 98 * effectively reduces the amount of available memory due to the effect of 99 * wrapping around while translating address to row/columns, for example in the 100 * 256MB module the upper 128MB get aliased with contents of the lower 101 * 128MB); normally this define should be used for devices with real 32-bit 102 * data path. 103 */ 104 #undef CONFIG_DDR_32BIT 105 106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 110 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 111 #define CONFIG_DDR_2T_TIMING 112 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 113 | DDRCDR_ODT \ 114 | DDRCDR_Q_DRN) 115 /* 0x80080001 */ 116 117 /* 118 * FLASH on the Local Bus 119 */ 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 122 #ifdef VME_CADDY2 123 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 124 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 125 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 126 (2 << BR_PS_SHIFT) | /* 16bit */ \ 127 BR_V) /* valid */ 128 129 #define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ 130 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 131 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ 132 #else 133 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 134 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 135 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 136 (2 << BR_PS_SHIFT) | /* 16bit */ \ 137 BR_V) /* valid */ 138 139 #define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ 140 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 141 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ 142 #endif 143 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 144 145 #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) 146 #define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) 147 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 148 #define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) 149 150 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 151 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 152 153 #undef CONFIG_SYS_FLASH_CHECKSUM 154 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 155 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 156 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 158 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 160 #define CONFIG_SYS_RAMBOOT 161 #else 162 #undef CONFIG_SYS_RAMBOOT 163 #endif 164 165 #define CONFIG_SYS_INIT_RAM_LOCK 1 166 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 167 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 168 169 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 170 GENERATED_GBL_DATA_SIZE) 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172 173 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 174 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */ 175 176 /* 177 * Local Bus LCRR and LBCR regs 178 * LCRR: no DLL bypass, Clock divider is 4 179 * External Local Bus rate is 180 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 181 */ 182 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 183 #define CONFIG_SYS_LBC_LBCR 0x00000000 184 185 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 186 187 /* 188 * Serial Port 189 */ 190 #define CONFIG_CONS_INDEX 1 191 #define CONFIG_SYS_NS16550 192 #define CONFIG_SYS_NS16550_SERIAL 193 #define CONFIG_SYS_NS16550_REG_SIZE 1 194 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 195 196 #define CONFIG_SYS_BAUDRATE_TABLE \ 197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 198 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 201 202 #define CONFIG_CMDLINE_EDITING /* add command line history */ 203 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 204 /* Use the HUSH parser */ 205 #define CONFIG_SYS_HUSH_PARSER 206 #ifdef CONFIG_SYS_HUSH_PARSER 207 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 208 #endif 209 210 /* pass open firmware flat tree */ 211 #define CONFIG_OF_LIBFDT 212 #define CONFIG_OF_BOARD_SETUP 213 #define CONFIG_OF_STDOUT_VIA_ALIAS 214 215 /* I2C */ 216 #define CONFIG_I2C_MULTI_BUS 217 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 218 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 219 #define CONFIG_FSL_I2C 220 #define CONFIG_I2C_CMD_TREE 221 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 222 #define CONFIG_SYS_I2C_SLAVE 0x7F 223 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 224 #define CONFIG_SYS_I2C1_OFFSET 0x3000 225 #define CONFIG_SYS_I2C2_OFFSET 0x3100 226 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 227 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 228 229 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 230 231 /* TSEC */ 232 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 233 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 234 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 235 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 236 237 /* 238 * General PCI 239 * Addresses are mapped 1-1. 240 */ 241 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 242 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 243 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 244 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 245 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 246 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 247 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 248 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 249 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 250 251 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 252 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 253 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 254 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 255 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 256 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 257 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 258 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 259 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 260 261 #if defined(CONFIG_PCI) 262 263 #define PCI_64BIT 264 #define PCI_ONE_PCI1 265 #if defined(PCI_64BIT) 266 #undef PCI_ALL_PCI1 267 #undef PCI_TWO_PCI1 268 #undef PCI_ONE_PCI1 269 #endif 270 271 #ifndef VME_CADDY2 272 #endif 273 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 274 275 #undef CONFIG_EEPRO100 276 #undef CONFIG_TULIP 277 278 #if !defined(CONFIG_PCI_PNP) 279 #define PCI_ENET0_IOADDR 0xFIXME 280 #define PCI_ENET0_MEMADDR 0xFIXME 281 #define PCI_IDSEL_NUMBER 0xFIXME 282 #endif 283 284 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 285 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 286 287 #endif /* CONFIG_PCI */ 288 289 /* 290 * TSEC configuration 291 */ 292 #ifdef VME_CADDY2 293 #define CONFIG_E1000 294 #else 295 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 296 #endif 297 298 #if defined(CONFIG_TSEC_ENET) 299 300 #define CONFIG_GMII /* MII PHY management */ 301 #define CONFIG_TSEC1 302 #define CONFIG_TSEC1_NAME "TSEC0" 303 #define CONFIG_TSEC2 304 #define CONFIG_TSEC2_NAME "TSEC1" 305 #define CONFIG_PHY_M88E1111 306 #define TSEC1_PHY_ADDR 0x08 307 #define TSEC2_PHY_ADDR 0x10 308 #define TSEC1_PHYIDX 0 309 #define TSEC2_PHYIDX 0 310 #define TSEC1_FLAGS TSEC_GIGABIT 311 #define TSEC2_FLAGS TSEC_GIGABIT 312 313 /* Options are: TSEC[0-1] */ 314 #define CONFIG_ETHPRIME "TSEC0" 315 316 #endif /* CONFIG_TSEC_ENET */ 317 318 /* 319 * Environment 320 */ 321 #ifndef CONFIG_SYS_RAMBOOT 322 #define CONFIG_ENV_IS_IN_FLASH 323 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 324 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 325 #define CONFIG_ENV_SIZE 0x2000 326 327 /* Address and size of Redundant Environment Sector */ 328 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 329 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 330 331 #else 332 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 333 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 335 #define CONFIG_ENV_SIZE 0x2000 336 #endif 337 338 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 339 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 340 341 /* 342 * BOOTP options 343 */ 344 #define CONFIG_BOOTP_BOOTFILESIZE 345 #define CONFIG_BOOTP_BOOTPATH 346 #define CONFIG_BOOTP_GATEWAY 347 #define CONFIG_BOOTP_HOSTNAME 348 349 /* 350 * Command line configuration. 351 */ 352 #include <config_cmd_default.h> 353 354 #define CONFIG_CMD_I2C 355 #define CONFIG_CMD_MII 356 #define CONFIG_CMD_PING 357 #define CONFIG_CMD_DATE 358 #define CONFIG_SYS_RTC_BUS_NUM 0x01 359 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 360 #define CONFIG_RTC_RX8025 361 #define CONFIG_CMD_TSI148 362 363 #if defined(CONFIG_PCI) 364 #define CONFIG_CMD_PCI 365 #endif 366 367 #if defined(CONFIG_SYS_RAMBOOT) 368 #undef CONFIG_CMD_ENV 369 #undef CONFIG_CMD_LOADS 370 #endif 371 372 #define CONFIG_CMD_ELF 373 /* Pass Ethernet MAC to VxWorks */ 374 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 375 376 #undef CONFIG_WATCHDOG /* watchdog disabled */ 377 378 /* 379 * Miscellaneous configurable options 380 */ 381 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 382 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 383 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 384 385 #if defined(CONFIG_CMD_KGDB) 386 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 387 #else 388 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 389 #endif 390 391 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 392 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 393 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 394 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 395 396 /* 397 * For booting Linux, the board info and command line data 398 * have to be in the first 256 MB of memory, since this is 399 * the maximum mapped by the Linux kernel during initialization. 400 */ 401 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 402 403 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 404 405 #define CONFIG_SYS_HRCW_LOW (\ 406 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 407 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 408 HRCWL_CSB_TO_CLKIN |\ 409 HRCWL_VCO_1X2 |\ 410 HRCWL_CORE_TO_CSB_2X1) 411 412 #if defined(PCI_64BIT) 413 #define CONFIG_SYS_HRCW_HIGH (\ 414 HRCWH_PCI_HOST |\ 415 HRCWH_64_BIT_PCI |\ 416 HRCWH_PCI1_ARBITER_ENABLE |\ 417 HRCWH_PCI2_ARBITER_DISABLE |\ 418 HRCWH_CORE_ENABLE |\ 419 HRCWH_FROM_0X00000100 |\ 420 HRCWH_BOOTSEQ_DISABLE |\ 421 HRCWH_SW_WATCHDOG_DISABLE |\ 422 HRCWH_ROM_LOC_LOCAL_16BIT |\ 423 HRCWH_TSEC1M_IN_GMII |\ 424 HRCWH_TSEC2M_IN_GMII) 425 #else 426 #define CONFIG_SYS_HRCW_HIGH (\ 427 HRCWH_PCI_HOST |\ 428 HRCWH_32_BIT_PCI |\ 429 HRCWH_PCI1_ARBITER_ENABLE |\ 430 HRCWH_PCI2_ARBITER_ENABLE |\ 431 HRCWH_CORE_ENABLE |\ 432 HRCWH_FROM_0X00000100 |\ 433 HRCWH_BOOTSEQ_DISABLE |\ 434 HRCWH_SW_WATCHDOG_DISABLE |\ 435 HRCWH_ROM_LOC_LOCAL_16BIT |\ 436 HRCWH_TSEC1M_IN_GMII |\ 437 HRCWH_TSEC2M_IN_GMII) 438 #endif 439 440 /* System IO Config */ 441 #define CONFIG_SYS_SICRH 0 442 #define CONFIG_SYS_SICRL SICRL_LDP_A 443 444 #define CONFIG_SYS_HID0_INIT 0x000000000 445 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 446 HID0_ENABLE_INSTRUCTION_CACHE) 447 448 #define CONFIG_SYS_HID2 HID2_HBE 449 450 #define CONFIG_SYS_GPIO1_PRELIM 451 #define CONFIG_SYS_GPIO1_DIR 0x00100000 452 #define CONFIG_SYS_GPIO1_DAT 0x00100000 453 454 #define CONFIG_SYS_GPIO2_PRELIM 455 #define CONFIG_SYS_GPIO2_DIR 0x78900000 456 #define CONFIG_SYS_GPIO2_DAT 0x70100000 457 458 #define CONFIG_HIGH_BATS /* High BATs supported */ 459 460 /* DDR @ 0x00000000 */ 461 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 462 BATL_MEMCOHERENCE) 463 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 464 BATU_VS | BATU_VP) 465 466 /* PCI @ 0x80000000 */ 467 #ifdef CONFIG_PCI 468 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 469 BATL_MEMCOHERENCE) 470 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 471 BATU_VS | BATU_VP) 472 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 473 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 474 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 475 BATU_VS | BATU_VP) 476 #else 477 #define CONFIG_SYS_IBAT1L (0) 478 #define CONFIG_SYS_IBAT1U (0) 479 #define CONFIG_SYS_IBAT2L (0) 480 #define CONFIG_SYS_IBAT2U (0) 481 #endif 482 483 #ifdef CONFIG_MPC83XX_PCI2 484 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 485 BATL_MEMCOHERENCE) 486 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 487 BATU_VS | BATU_VP) 488 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 489 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 490 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 491 BATU_VS | BATU_VP) 492 #else 493 #define CONFIG_SYS_IBAT3L (0) 494 #define CONFIG_SYS_IBAT3U (0) 495 #define CONFIG_SYS_IBAT4L (0) 496 #define CONFIG_SYS_IBAT4U (0) 497 #endif 498 499 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 500 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 501 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 502 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 503 BATU_VS | BATU_VP) 504 505 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 506 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 507 508 #if (CONFIG_SYS_DDR_SIZE == 512) 509 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 510 BATL_PP_RW | BATL_MEMCOHERENCE) 511 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 512 BATU_BL_256M | BATU_VS | BATU_VP) 513 #else 514 #define CONFIG_SYS_IBAT7L (0) 515 #define CONFIG_SYS_IBAT7U (0) 516 #endif 517 518 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 519 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 520 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 521 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 522 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 523 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 524 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 525 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 526 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 527 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 528 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 529 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 530 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 531 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 532 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 533 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 534 535 #if defined(CONFIG_CMD_KGDB) 536 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 537 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 538 #endif 539 540 /* 541 * Environment Configuration 542 */ 543 #define CONFIG_ENV_OVERWRITE 544 545 #if defined(CONFIG_TSEC_ENET) 546 #define CONFIG_HAS_ETH0 547 #define CONFIG_HAS_ETH1 548 #endif 549 550 #define CONFIG_HOSTNAME VME8349 551 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 552 #define CONFIG_BOOTFILE "uImage" 553 554 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 555 556 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 557 #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 558 559 #define CONFIG_BAUDRATE 9600 560 561 #define CONFIG_EXTRA_ENV_SETTINGS \ 562 "netdev=eth0\0" \ 563 "hostname=vme8349\0" \ 564 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 565 "nfsroot=${serverip}:${rootpath}\0" \ 566 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 567 "addip=setenv bootargs ${bootargs} " \ 568 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 569 ":${hostname}:${netdev}:off panic=1\0" \ 570 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 571 "flash_nfs=run nfsargs addip addtty;" \ 572 "bootm ${kernel_addr}\0" \ 573 "flash_self=run ramargs addip addtty;" \ 574 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 575 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 576 "bootm\0" \ 577 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 578 "update=protect off fff00000 fff3ffff; " \ 579 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 580 "upd=run load update\0" \ 581 "fdtaddr=780000\0" \ 582 "fdtfile=vme8349.dtb\0" \ 583 "" 584 585 #define CONFIG_NFSBOOTCOMMAND \ 586 "setenv bootargs root=/dev/nfs rw " \ 587 "nfsroot=$serverip:$rootpath " \ 588 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 589 "$netdev:off " \ 590 "console=$consoledev,$baudrate $othbootargs;" \ 591 "tftp $loadaddr $bootfile;" \ 592 "tftp $fdtaddr $fdtfile;" \ 593 "bootm $loadaddr - $fdtaddr" 594 595 #define CONFIG_RAMBOOTCOMMAND \ 596 "setenv bootargs root=/dev/ram rw " \ 597 "console=$consoledev,$baudrate $othbootargs;" \ 598 "tftp $ramdiskaddr $ramdiskfile;" \ 599 "tftp $loadaddr $bootfile;" \ 600 "tftp $fdtaddr $fdtfile;" \ 601 "bootm $loadaddr $ramdiskaddr $fdtaddr" 602 603 #define CONFIG_BOOTCOMMAND "run flash_self" 604 605 #ifndef __ASSEMBLY__ 606 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 607 unsigned char *buffer, int len); 608 #endif 609 610 #endif /* __CONFIG_H */ 611