xref: /rk3399_rockchip-uboot/include/configs/vct.h (revision 736fead8fdbf8a8407048bebc373cd551d01ec98)
1ae691e57SStefan Roese /*
2ae691e57SStefan Roese  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3ae691e57SStefan Roese  *
4ae691e57SStefan Roese  * This program is free software; you can redistribute it and/or
5ae691e57SStefan Roese  * modify it under the terms of the GNU General Public License as
6ae691e57SStefan Roese  * published by the Free Software Foundation; either version 2 of
7ae691e57SStefan Roese  * the License, or (at your option) any later version.
8ae691e57SStefan Roese  *
9ae691e57SStefan Roese  * This program is distributed in the hope that it will be useful,
10ae691e57SStefan Roese  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11ae691e57SStefan Roese  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12ae691e57SStefan Roese  * GNU General Public License for more details.
13ae691e57SStefan Roese  *
14ae691e57SStefan Roese  * You should have received a copy of the GNU General Public License
15ae691e57SStefan Roese  * along with this program; if not, write to the Free Software
16ae691e57SStefan Roese  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17ae691e57SStefan Roese  * MA 02111-1307 USA
18ae691e57SStefan Roese  */
19ae691e57SStefan Roese 
20ae691e57SStefan Roese /*
21ae691e57SStefan Roese  * This file contains the configuration parameters for the VCT board
22ae691e57SStefan Roese  * family:
23ae691e57SStefan Roese  *
24ae691e57SStefan Roese  * vct_premium
25ae691e57SStefan Roese  * vct_premium_small
26ae691e57SStefan Roese  * vct_premium_onenand
27ae691e57SStefan Roese  * vct_premium_onenand_small
28ae691e57SStefan Roese  * vct_platinum
29ae691e57SStefan Roese  * vct_platinum_small
30ae691e57SStefan Roese  * vct_platinum_onenand
31ae691e57SStefan Roese  * vct_platinum_onenand_small
32ae691e57SStefan Roese  * vct_platinumavc
33ae691e57SStefan Roese  * vct_platinumavc_small
34ae691e57SStefan Roese  * vct_platinumavc_onenand
35ae691e57SStefan Roese  * vct_platinumavc_onenand_small
36ae691e57SStefan Roese  */
37ae691e57SStefan Roese 
38ae691e57SStefan Roese #ifndef __CONFIG_H
39ae691e57SStefan Roese #define __CONFIG_H
40ae691e57SStefan Roese 
41ae691e57SStefan Roese #define CONFIG_MIPS32				/* MIPS 4Kc CPU core	*/
42ae691e57SStefan Roese #define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
43ae691e57SStefan Roese #define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
44ae691e57SStefan Roese #define CONFIG_SYS_HZ			1000
45ae691e57SStefan Roese 
46ae691e57SStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
47ae691e57SStefan Roese 
48ae691e57SStefan Roese #define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
49ae691e57SStefan Roese #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
50ae691e57SStefan Roese #define CONFIG_STACKSIZE		(256 << 10)
51ae691e57SStefan Roese #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
52ae691e57SStefan Roese #define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
53ae691e57SStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
54ae691e57SStefan Roese 
55ae691e57SStefan Roese #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
56ae691e57SStefan Roese #define CONFIG_VCT_NOR
57ae691e57SStefan Roese #else
58ae691e57SStefan Roese #define CONFIG_SYS_NO_FLASH
59ae691e57SStefan Roese #endif
60ae691e57SStefan Roese 
61ae691e57SStefan Roese /*
62ae691e57SStefan Roese  * UART
63ae691e57SStefan Roese  */
64294f10caSDetlev Zundel #ifdef CONFIG_VCT_PLATINUMAVC
65294f10caSDetlev Zundel #define UART_1_BASE		0xBDC30000
66294f10caSDetlev Zundel #else
67294f10caSDetlev Zundel #define UART_1_BASE		0xBF89C000
68294f10caSDetlev Zundel #endif
69294f10caSDetlev Zundel 
70294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_SERIAL
71294f10caSDetlev Zundel #define CONFIG_SYS_NS16550
72294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_REG_SIZE	-4
73294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_COM1		UART_1_BASE
74294f10caSDetlev Zundel #define CONFIG_CONS_INDEX		1
75294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_CLK		921600
76ae691e57SStefan Roese #define CONFIG_BAUDRATE			115200
77ae691e57SStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
78ae691e57SStefan Roese 
79ae691e57SStefan Roese /*
80ae691e57SStefan Roese  * SDRAM
81ae691e57SStefan Roese  */
82ae691e57SStefan Roese #define CONFIG_SYS_SDRAM_BASE		0x80000000
83ae691e57SStefan Roese #define CONFIG_SYS_MBYTES_SDRAM		128
84ae691e57SStefan Roese #define CONFIG_SYS_MEMTEST_START	0x80200000
85ae691e57SStefan Roese #define CONFIG_SYS_MEMTEST_END		0x80400000
86ae691e57SStefan Roese #define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
87ae691e57SStefan Roese 
88ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
89ae691e57SStefan Roese /*
90ae691e57SStefan Roese  * SMSC91C11x Network Card
91ae691e57SStefan Roese  */
92*736fead8SBen Warren #define CONFIG_SMC911X
93*736fead8SBen Warren #define CONFIG_SMC911X_BASE	0x00000000
94*736fead8SBen Warren #define CONFIG_SMC911X_32_BIT
95ae691e57SStefan Roese #define CONFIG_NET_RETRY_COUNT		20
96*736fead8SBen Warren #define CONFIG_NET_MULTI
97ae691e57SStefan Roese #endif
98ae691e57SStefan Roese 
99ae691e57SStefan Roese /*
100ae691e57SStefan Roese  * Commands
101ae691e57SStefan Roese  */
102ae691e57SStefan Roese #include <config_cmd_default.h>
103ae691e57SStefan Roese 
104ae691e57SStefan Roese #define CONFIG_CMD_DHCP
105ae691e57SStefan Roese #define CONFIG_CMD_ELF
106ae691e57SStefan Roese #define CONFIG_CMD_EEPROM
107ae691e57SStefan Roese #define CONFIG_CMD_I2C
108ae691e57SStefan Roese 
109ae691e57SStefan Roese /*
110ae691e57SStefan Roese  * Only Premium/Platinum have ethernet support right now
111ae691e57SStefan Roese  */
112ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
113ae691e57SStefan Roese #define CONFIG_CMD_PING
114ae691e57SStefan Roese #define CONFIG_CMD_SNTP
115ae691e57SStefan Roese #else
116ae691e57SStefan Roese #undef CONFIG_CMD_NET
117ae691e57SStefan Roese #endif
118ae691e57SStefan Roese 
119ae691e57SStefan Roese /*
120ae691e57SStefan Roese  * Only Premium/Platinum have USB-EHCI support right now
121ae691e57SStefan Roese  */
122ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
123ae691e57SStefan Roese #define CONFIG_CMD_USB
124ae691e57SStefan Roese #define CONFIG_CMD_FAT
125ae691e57SStefan Roese #endif
126ae691e57SStefan Roese 
127ae691e57SStefan Roese #if defined(CONFIG_CMD_USB)
128ae691e57SStefan Roese #define CONFIG_USB_STORAGE
129ae691e57SStefan Roese #define CONFIG_DOS_PARTITION
130ae691e57SStefan Roese #define CONFIG_ISO_PARTITION
131ae691e57SStefan Roese 
132ae691e57SStefan Roese #define CONFIG_SUPPORT_VFAT
133ae691e57SStefan Roese 
134ae691e57SStefan Roese /*
135ae691e57SStefan Roese  * USB/EHCI
136ae691e57SStefan Roese  */
137ae691e57SStefan Roese #define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
138ae691e57SStefan Roese #define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
139ae691e57SStefan Roese #define CONFIG_EHCI_DCACHE		/* with dcache handling support	*/
140ae691e57SStefan Roese #define CONFIG_EHCI_MMIO_BIG_ENDIAN
141ae691e57SStefan Roese #define CONFIG_EHCI_DESC_BIG_ENDIAN
142ae691e57SStefan Roese #define CONFIG_EHCI_IS_TDI
143ae691e57SStefan Roese #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
144ae691e57SStefan Roese #endif /* CONFIG_CMD_USB */
145ae691e57SStefan Roese 
146ae691e57SStefan Roese #if !defined(CONFIG_VCT_NOR)
147ae691e57SStefan Roese #undef CONFIG_CMD_FLASH
148ae691e57SStefan Roese #undef CONFIG_CMD_IMLS
149ae691e57SStefan Roese #endif
150ae691e57SStefan Roese 
151ae691e57SStefan Roese #if defined(CONFIG_VCT_NAND)
152ae691e57SStefan Roese #define CONFIG_CMD_NAND
153ae691e57SStefan Roese #endif
154ae691e57SStefan Roese 
155ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
156ae691e57SStefan Roese #define CONFIG_CMD_ONENAND
157ae691e57SStefan Roese #endif
158ae691e57SStefan Roese 
159ae691e57SStefan Roese /*
160ae691e57SStefan Roese  * BOOTP options
161ae691e57SStefan Roese  */
162ae691e57SStefan Roese #define CONFIG_BOOTP_BOOTFILESIZE
163ae691e57SStefan Roese #define CONFIG_BOOTP_BOOTPATH
164ae691e57SStefan Roese #define CONFIG_BOOTP_GATEWAY
165ae691e57SStefan Roese #define CONFIG_BOOTP_HOSTNAME
166ae691e57SStefan Roese #define CONFIG_BOOTP_SUBNETMASK
167ae691e57SStefan Roese 
168ae691e57SStefan Roese /*
169ae691e57SStefan Roese  * Miscellaneous configurable options
170ae691e57SStefan Roese  */
171ae691e57SStefan Roese #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
172ae691e57SStefan Roese #define CONFIG_SYS_PROMPT	"VCT# "		/* Monitor Command Prompt	*/
173ae691e57SStefan Roese #define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
174ae691e57SStefan Roese #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
175ae691e57SStefan Roese 				 sizeof(CONFIG_SYS_PROMPT) + 16)
176ae691e57SStefan Roese #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
177ae691e57SStefan Roese #define CONFIG_TIMESTAMP			/* Print image info with timestamp */
178ae691e57SStefan Roese #define CONFIG_CMDLINE_EDITING			/* add command line history	*/
179ae691e57SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
180ae691e57SStefan Roese 
181ae691e57SStefan Roese /*
182ae691e57SStefan Roese  * FLASH and environment organization
183ae691e57SStefan Roese  */
184ae691e57SStefan Roese #if defined(CONFIG_VCT_NOR)
185ae691e57SStefan Roese #define CONFIG_ENV_IS_IN_FLASH
186ae691e57SStefan Roese #define CONFIG_FLASH_NOT_MEM_MAPPED
187ae691e57SStefan Roese 
188ae691e57SStefan Roese /*
189ae691e57SStefan Roese  * We need special accessor functions for the CFI FLASH driver. This
190ae691e57SStefan Roese  * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
191ae691e57SStefan Roese  */
192ae691e57SStefan Roese #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
193ae691e57SStefan Roese 
194ae691e57SStefan Roese /*
195ae691e57SStefan Roese  * For the non-memory-mapped NOR FLASH, we need to define the
196ae691e57SStefan Roese  * NOR FLASH area. This can't be detected via the addr2info()
197ae691e57SStefan Roese  * function, since we check for flash access in the very early
198ae691e57SStefan Roese  * U-Boot code, before the NOR FLASH is detected.
199ae691e57SStefan Roese  */
200ae691e57SStefan Roese #define CONFIG_FLASH_BASE		0xb0000000
201ae691e57SStefan Roese #define CONFIG_FLASH_END		0xbfffffff
202ae691e57SStefan Roese 
203ae691e57SStefan Roese /*
204ae691e57SStefan Roese  * CFI driver settings
205ae691e57SStefan Roese  */
206ae691e57SStefan Roese #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
207ae691e57SStefan Roese #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
208ae691e57SStefan Roese #define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
209ae691e57SStefan Roese #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
210ae691e57SStefan Roese 
211ae691e57SStefan Roese #define CONFIG_SYS_FLASH_BASE		0xb0000000
212ae691e57SStefan Roese #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
213ae691e57SStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
214ae691e57SStefan Roese #define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
215ae691e57SStefan Roese 
216ae691e57SStefan Roese #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
217ae691e57SStefan Roese #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
218ae691e57SStefan Roese 
219ae691e57SStefan Roese #ifdef CONFIG_ENV_IS_IN_FLASH
220ae691e57SStefan Roese #define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
221ae691e57SStefan Roese #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
222ae691e57SStefan Roese #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
223ae691e57SStefan Roese 
224ae691e57SStefan Roese /* Address and size of Redundant Environment Sector	*/
225ae691e57SStefan Roese #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
226ae691e57SStefan Roese #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
227ae691e57SStefan Roese #endif /* CONFIG_ENV_IS_IN_FLASH */
228ae691e57SStefan Roese #endif /* CONFIG_VCT_NOR */
229ae691e57SStefan Roese 
230ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
231ae691e57SStefan Roese #define CONFIG_USE_ONENAND_BOARD_INIT
232ae691e57SStefan Roese #define	CONFIG_ENV_IS_IN_ONENAND
233ae691e57SStefan Roese #define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
234ae691e57SStefan Roese #define CONFIG_SYS_FLASH_BASE		0x00000000
235ae691e57SStefan Roese #define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
236ae691e57SStefan Roese #define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
237ae691e57SStefan Roese #endif /* CONFIG_VCT_ONENAND */
238ae691e57SStefan Roese 
239ae691e57SStefan Roese /*
240ae691e57SStefan Roese  * Cache Configuration
241ae691e57SStefan Roese  */
242ae691e57SStefan Roese #define CONFIG_SYS_DCACHE_SIZE		16384
243ae691e57SStefan Roese #define CONFIG_SYS_ICACHE_SIZE		16384
244ae691e57SStefan Roese #define CONFIG_SYS_CACHELINE_SIZE	32
245ae691e57SStefan Roese 
246ae691e57SStefan Roese /*
247ae691e57SStefan Roese  * I2C/EEPROM
248ae691e57SStefan Roese  */
249ae691e57SStefan Roese #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
250ae691e57SStefan Roese #define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
251ae691e57SStefan Roese 
252ae691e57SStefan Roese #define CONFIG_SYS_I2C_SPEED		83000	/* 83 kHz is supposed to work	*/
253ae691e57SStefan Roese #define CONFIG_SYS_I2C_SLAVE		0x7f
254ae691e57SStefan Roese 
255ae691e57SStefan Roese /*
256ae691e57SStefan Roese  * Software (bit-bang) I2C driver configuration
257ae691e57SStefan Roese  */
258ae691e57SStefan Roese #define CONFIG_SYS_GPIO_I2C_SCL		11
259ae691e57SStefan Roese #define CONFIG_SYS_GPIO_I2C_SDA		10
260ae691e57SStefan Roese 
261ae691e57SStefan Roese #ifndef __ASSEMBLY__
262ae691e57SStefan Roese int vct_gpio_dir(int pin, int dir);
263ae691e57SStefan Roese void vct_gpio_set(int pin, int val);
264ae691e57SStefan Roese int vct_gpio_get(int pin);
265ae691e57SStefan Roese #endif
266ae691e57SStefan Roese 
267ae691e57SStefan Roese #define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
268ae691e57SStefan Roese #define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
269ae691e57SStefan Roese #define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
270ae691e57SStefan Roese #define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
271ae691e57SStefan Roese #define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
272ae691e57SStefan Roese #define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
273ae691e57SStefan Roese #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
274ae691e57SStefan Roese 
275ae691e57SStefan Roese #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
276ae691e57SStefan Roese /* CAT24WC32 */
277ae691e57SStefan Roese #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
278ae691e57SStefan Roese #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
279ae691e57SStefan Roese 					/* 32 byte page write mode using*/
280ae691e57SStefan Roese 					/* last 5 bits of the address	*/
281ae691e57SStefan Roese #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
282ae691e57SStefan Roese 
283ae691e57SStefan Roese #define CONFIG_BOOTCOMMAND	"run test3"
284ae691e57SStefan Roese #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
285ae691e57SStefan Roese 
286ae691e57SStefan Roese /*
287ae691e57SStefan Roese  * Needed for 64bit printf format
288ae691e57SStefan Roese  */
289ae691e57SStefan Roese #define CONFIG_SYS_64BIT_VSPRINTF	1
290ae691e57SStefan Roese #define CONFIG_SYS_64BIT_STRTOUL	1
291ae691e57SStefan Roese 
292ae691e57SStefan Roese /*
293ae691e57SStefan Roese  * UBI configuration
294ae691e57SStefan Roese  */
295ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
296ae691e57SStefan Roese #define CONFIG_SYS_USE_UBI
297ae691e57SStefan Roese #define	CONFIG_CMD_JFFS2
298ae691e57SStefan Roese #define	CONFIG_CMD_UBI
299ae691e57SStefan Roese #define	CONFIG_RBTREE
300942556a9SStefan Roese #define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
301ae691e57SStefan Roese #define CONFIG_MTD_PARTITIONS
30268d7d651SStefan Roese #define CONFIG_CMD_MTDPARTS
303ae691e57SStefan Roese 
304ae691e57SStefan Roese #define MTDIDS_DEFAULT		"onenand0=onenand"
305ae691e57SStefan Roese #define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(u-boot),"	\
306ae691e57SStefan Roese 					"128k(env),"		\
307ae691e57SStefan Roese 					"20m(kernel),"		\
308ae691e57SStefan Roese 					"-(rootfs)"
309ae691e57SStefan Roese #endif
310ae691e57SStefan Roese 
311ae691e57SStefan Roese /*
312ae691e57SStefan Roese  * We need a small, stripped down image to fit into the first 128k OneNAND
313ae691e57SStefan Roese  * erase block (gzipped). This image only needs basic commands for FLASH
314ae691e57SStefan Roese  * (NOR/OneNAND) usage and Linux kernel booting.
315ae691e57SStefan Roese  */
316ae691e57SStefan Roese #if defined(CONFIG_VCT_SMALL_IMAGE)
317ae691e57SStefan Roese #undef CONFIG_CMD_ASKENV
31874de7aefSWolfgang Denk #undef CONFIG_CMD_BDI
31974de7aefSWolfgang Denk #undef CONFIG_CMD_BEDBUG
32074de7aefSWolfgang Denk #undef CONFIG_CMD_CACHE
32174de7aefSWolfgang Denk #undef CONFIG_CMD_CONSOLE
322ae691e57SStefan Roese #undef CONFIG_CMD_CRC32
323ae691e57SStefan Roese #undef CONFIG_CMD_DHCP
324ae691e57SStefan Roese #undef CONFIG_CMD_EEPROM
32574de7aefSWolfgang Denk #undef CONFIG_CMD_EEPROM
32674de7aefSWolfgang Denk #undef CONFIG_CMD_ELF
32774de7aefSWolfgang Denk #undef CONFIG_CMD_FAT
328ae691e57SStefan Roese #undef CONFIG_CMD_I2C
32974de7aefSWolfgang Denk #undef CONFIG_CMD_I2C
33074de7aefSWolfgang Denk #undef CONFIG_CMD_IRQ
33174de7aefSWolfgang Denk #undef CONFIG_CMD_ITEST
332ae691e57SStefan Roese #undef CONFIG_CMD_LOADB
333ae691e57SStefan Roese #undef CONFIG_CMD_LOADS
334ae691e57SStefan Roese #undef CONFIG_CMD_LOADY
33574de7aefSWolfgang Denk #undef CONFIG_CMD_MII
33674de7aefSWolfgang Denk #undef CONFIG_CMD_MISC
33774de7aefSWolfgang Denk #undef CONFIG_CMD_NET
33874de7aefSWolfgang Denk #undef CONFIG_CMD_PING
33974de7aefSWolfgang Denk #undef CONFIG_CMD_REGINFO
34074de7aefSWolfgang Denk #undef CONFIG_CMD_SNTP
34174de7aefSWolfgang Denk #undef CONFIG_CMD_SOURCE
34274de7aefSWolfgang Denk #undef CONFIG_CMD_STRINGS
34374de7aefSWolfgang Denk #undef CONFIG_CMD_TERMINAL
344ae691e57SStefan Roese #undef CONFIG_CMD_USB
345ae691e57SStefan Roese 
346*736fead8SBen Warren #undef CONFIG_SMC911X
347ae691e57SStefan Roese #undef CONFIG_SOFT_I2C
34874de7aefSWolfgang Denk #undef CONFIG_SOURCE
349ae691e57SStefan Roese #undef CONFIG_SYS_LONGHELP
350ae691e57SStefan Roese #undef CONFIG_TIMESTAMP
351ae691e57SStefan Roese #endif /* CONFIG_VCT_SMALL_IMAGE */
352ae691e57SStefan Roese 
353ae691e57SStefan Roese #endif  /* __CONFIG_H */
354