xref: /rk3399_rockchip-uboot/include/configs/vct.h (revision 1a4596601fd395f3afb8f82f3f840c5e00bdd57a)
1ae691e57SStefan Roese /*
2ae691e57SStefan Roese  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3ae691e57SStefan Roese  *
4*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5ae691e57SStefan Roese  */
6ae691e57SStefan Roese 
7ae691e57SStefan Roese /*
8ae691e57SStefan Roese  * This file contains the configuration parameters for the VCT board
9ae691e57SStefan Roese  * family:
10ae691e57SStefan Roese  *
11ae691e57SStefan Roese  * vct_premium
12ae691e57SStefan Roese  * vct_premium_small
13ae691e57SStefan Roese  * vct_premium_onenand
14ae691e57SStefan Roese  * vct_premium_onenand_small
15ae691e57SStefan Roese  * vct_platinum
16ae691e57SStefan Roese  * vct_platinum_small
17ae691e57SStefan Roese  * vct_platinum_onenand
18ae691e57SStefan Roese  * vct_platinum_onenand_small
19ae691e57SStefan Roese  * vct_platinumavc
20ae691e57SStefan Roese  * vct_platinumavc_small
21ae691e57SStefan Roese  * vct_platinumavc_onenand
22ae691e57SStefan Roese  * vct_platinumavc_onenand_small
23ae691e57SStefan Roese  */
24ae691e57SStefan Roese 
25ae691e57SStefan Roese #ifndef __CONFIG_H
26ae691e57SStefan Roese #define __CONFIG_H
27ae691e57SStefan Roese 
28ae691e57SStefan Roese #define CONFIG_MIPS32				/* MIPS 4Kc CPU core	*/
29ae691e57SStefan Roese #define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
30ae691e57SStefan Roese #define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
31ae691e57SStefan Roese #define CONFIG_SYS_HZ			1000
32ae691e57SStefan Roese 
33ae691e57SStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
34ae691e57SStefan Roese 
3514d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
36ae691e57SStefan Roese #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
37ae691e57SStefan Roese #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
38ae691e57SStefan Roese #define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
39ae691e57SStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
40ae691e57SStefan Roese 
41ae691e57SStefan Roese #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
42ae691e57SStefan Roese #define CONFIG_VCT_NOR
43ae691e57SStefan Roese #else
44ae691e57SStefan Roese #define CONFIG_SYS_NO_FLASH
45ae691e57SStefan Roese #endif
46ae691e57SStefan Roese 
47ae691e57SStefan Roese /*
48ae691e57SStefan Roese  * UART
49ae691e57SStefan Roese  */
50294f10caSDetlev Zundel #ifdef CONFIG_VCT_PLATINUMAVC
51294f10caSDetlev Zundel #define UART_1_BASE		0xBDC30000
52294f10caSDetlev Zundel #else
53294f10caSDetlev Zundel #define UART_1_BASE		0xBF89C000
54294f10caSDetlev Zundel #endif
55294f10caSDetlev Zundel 
56294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_SERIAL
57294f10caSDetlev Zundel #define CONFIG_SYS_NS16550
58294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_REG_SIZE	-4
59294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_COM1		UART_1_BASE
60294f10caSDetlev Zundel #define CONFIG_CONS_INDEX		1
61294f10caSDetlev Zundel #define CONFIG_SYS_NS16550_CLK		921600
62ae691e57SStefan Roese #define CONFIG_BAUDRATE			115200
63ae691e57SStefan Roese 
64ae691e57SStefan Roese /*
65ae691e57SStefan Roese  * SDRAM
66ae691e57SStefan Roese  */
67ae691e57SStefan Roese #define CONFIG_SYS_SDRAM_BASE		0x80000000
68ae691e57SStefan Roese #define CONFIG_SYS_MBYTES_SDRAM		128
69ae691e57SStefan Roese #define CONFIG_SYS_MEMTEST_START	0x80200000
70ae691e57SStefan Roese #define CONFIG_SYS_MEMTEST_END		0x80400000
71ae691e57SStefan Roese #define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
72ae691e57SStefan Roese 
73ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
74ae691e57SStefan Roese /*
75ae691e57SStefan Roese  * SMSC91C11x Network Card
76ae691e57SStefan Roese  */
77736fead8SBen Warren #define CONFIG_SMC911X
78736fead8SBen Warren #define CONFIG_SMC911X_BASE	0x00000000
79736fead8SBen Warren #define CONFIG_SMC911X_32_BIT
80ae691e57SStefan Roese #define CONFIG_NET_RETRY_COUNT		20
81ae691e57SStefan Roese #endif
82ae691e57SStefan Roese 
83ae691e57SStefan Roese /*
84ae691e57SStefan Roese  * Commands
85ae691e57SStefan Roese  */
86ae691e57SStefan Roese #include <config_cmd_default.h>
87ae691e57SStefan Roese 
88ae691e57SStefan Roese #define CONFIG_CMD_DHCP
89ae691e57SStefan Roese #define CONFIG_CMD_ELF
90ae691e57SStefan Roese #define CONFIG_CMD_EEPROM
91ae691e57SStefan Roese #define CONFIG_CMD_I2C
92ae691e57SStefan Roese 
93ae691e57SStefan Roese /*
94ae691e57SStefan Roese  * Only Premium/Platinum have ethernet support right now
95ae691e57SStefan Roese  */
96383015b2SDaniel Schwierzeck #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
97383015b2SDaniel Schwierzeck 	!defined(CONFIG_VCT_SMALL_IMAGE)
98ae691e57SStefan Roese #define CONFIG_CMD_PING
99ae691e57SStefan Roese #define CONFIG_CMD_SNTP
100ae691e57SStefan Roese #else
101ae691e57SStefan Roese #undef CONFIG_CMD_NET
102383015b2SDaniel Schwierzeck #undef CONFIG_CMD_NFS
103ae691e57SStefan Roese #endif
104ae691e57SStefan Roese 
105ae691e57SStefan Roese /*
106ae691e57SStefan Roese  * Only Premium/Platinum have USB-EHCI support right now
107ae691e57SStefan Roese  */
108383015b2SDaniel Schwierzeck #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
109383015b2SDaniel Schwierzeck 	!defined(CONFIG_VCT_SMALL_IMAGE)
110ae691e57SStefan Roese #define CONFIG_CMD_USB
111ae691e57SStefan Roese #define CONFIG_CMD_FAT
112ae691e57SStefan Roese #endif
113ae691e57SStefan Roese 
114ae691e57SStefan Roese #if defined(CONFIG_CMD_USB)
115ae691e57SStefan Roese #define CONFIG_USB_STORAGE
116ae691e57SStefan Roese #define CONFIG_DOS_PARTITION
117ae691e57SStefan Roese #define CONFIG_ISO_PARTITION
118ae691e57SStefan Roese 
119ae691e57SStefan Roese #define CONFIG_SUPPORT_VFAT
120ae691e57SStefan Roese 
121ae691e57SStefan Roese /*
122ae691e57SStefan Roese  * USB/EHCI
123ae691e57SStefan Roese  */
124ae691e57SStefan Roese #define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
125ae691e57SStefan Roese #define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
126ae691e57SStefan Roese #define CONFIG_EHCI_MMIO_BIG_ENDIAN
127ae691e57SStefan Roese #define CONFIG_EHCI_DESC_BIG_ENDIAN
128ae691e57SStefan Roese #define CONFIG_EHCI_IS_TDI
129ae691e57SStefan Roese #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
130ae691e57SStefan Roese #endif /* CONFIG_CMD_USB */
131ae691e57SStefan Roese 
132ae691e57SStefan Roese #if !defined(CONFIG_VCT_NOR)
133ae691e57SStefan Roese #undef CONFIG_CMD_FLASH
134ae691e57SStefan Roese #undef CONFIG_CMD_IMLS
135ae691e57SStefan Roese #endif
136ae691e57SStefan Roese 
137ae691e57SStefan Roese #if defined(CONFIG_VCT_NAND)
138ae691e57SStefan Roese #define CONFIG_CMD_NAND
139ae691e57SStefan Roese #endif
140ae691e57SStefan Roese 
141ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
142ae691e57SStefan Roese #define CONFIG_CMD_ONENAND
143ae691e57SStefan Roese #endif
144ae691e57SStefan Roese 
145ae691e57SStefan Roese /*
146ae691e57SStefan Roese  * BOOTP options
147ae691e57SStefan Roese  */
148ae691e57SStefan Roese #define CONFIG_BOOTP_BOOTFILESIZE
149ae691e57SStefan Roese #define CONFIG_BOOTP_BOOTPATH
150ae691e57SStefan Roese #define CONFIG_BOOTP_GATEWAY
151ae691e57SStefan Roese #define CONFIG_BOOTP_HOSTNAME
152ae691e57SStefan Roese #define CONFIG_BOOTP_SUBNETMASK
153ae691e57SStefan Roese 
154ae691e57SStefan Roese /*
155ae691e57SStefan Roese  * Miscellaneous configurable options
156ae691e57SStefan Roese  */
157ae691e57SStefan Roese #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
158ae691e57SStefan Roese #define CONFIG_SYS_PROMPT	"VCT# "		/* Monitor Command Prompt	*/
159ae691e57SStefan Roese #define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
160ae691e57SStefan Roese #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
161ae691e57SStefan Roese 				 sizeof(CONFIG_SYS_PROMPT) + 16)
162ae691e57SStefan Roese #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
163ae691e57SStefan Roese #define CONFIG_TIMESTAMP			/* Print image info with timestamp */
164ae691e57SStefan Roese #define CONFIG_CMDLINE_EDITING			/* add command line history	*/
165ae691e57SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
166ae691e57SStefan Roese 
167ae691e57SStefan Roese /*
168ae691e57SStefan Roese  * FLASH and environment organization
169ae691e57SStefan Roese  */
170ae691e57SStefan Roese #if defined(CONFIG_VCT_NOR)
171ae691e57SStefan Roese #define CONFIG_ENV_IS_IN_FLASH
172ae691e57SStefan Roese #define CONFIG_FLASH_NOT_MEM_MAPPED
173ae691e57SStefan Roese 
174ae691e57SStefan Roese /*
175ae691e57SStefan Roese  * We need special accessor functions for the CFI FLASH driver. This
176ae691e57SStefan Roese  * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
177ae691e57SStefan Roese  */
178ae691e57SStefan Roese #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
179ae691e57SStefan Roese 
180ae691e57SStefan Roese /*
181ae691e57SStefan Roese  * For the non-memory-mapped NOR FLASH, we need to define the
182ae691e57SStefan Roese  * NOR FLASH area. This can't be detected via the addr2info()
183ae691e57SStefan Roese  * function, since we check for flash access in the very early
184ae691e57SStefan Roese  * U-Boot code, before the NOR FLASH is detected.
185ae691e57SStefan Roese  */
186ae691e57SStefan Roese #define CONFIG_FLASH_BASE		0xb0000000
187ae691e57SStefan Roese #define CONFIG_FLASH_END		0xbfffffff
188ae691e57SStefan Roese 
189ae691e57SStefan Roese /*
190ae691e57SStefan Roese  * CFI driver settings
191ae691e57SStefan Roese  */
192ae691e57SStefan Roese #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
193ae691e57SStefan Roese #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
194ae691e57SStefan Roese #define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
195ae691e57SStefan Roese #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
196ae691e57SStefan Roese 
197ae691e57SStefan Roese #define CONFIG_SYS_FLASH_BASE		0xb0000000
198ae691e57SStefan Roese #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
199ae691e57SStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
200ae691e57SStefan Roese #define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
201ae691e57SStefan Roese 
202ae691e57SStefan Roese #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
203ae691e57SStefan Roese #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
204ae691e57SStefan Roese 
205ae691e57SStefan Roese #ifdef CONFIG_ENV_IS_IN_FLASH
206ae691e57SStefan Roese #define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
207ae691e57SStefan Roese #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
208ae691e57SStefan Roese #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
209ae691e57SStefan Roese 
210ae691e57SStefan Roese /* Address and size of Redundant Environment Sector	*/
211ae691e57SStefan Roese #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
212ae691e57SStefan Roese #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
213ae691e57SStefan Roese #endif /* CONFIG_ENV_IS_IN_FLASH */
214ae691e57SStefan Roese #endif /* CONFIG_VCT_NOR */
215ae691e57SStefan Roese 
216ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
217ae691e57SStefan Roese #define CONFIG_USE_ONENAND_BOARD_INIT
218ae691e57SStefan Roese #define	CONFIG_ENV_IS_IN_ONENAND
219ae691e57SStefan Roese #define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
220ae691e57SStefan Roese #define CONFIG_SYS_FLASH_BASE		0x00000000
221ae691e57SStefan Roese #define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
222ae691e57SStefan Roese #define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
223ae691e57SStefan Roese #endif /* CONFIG_VCT_ONENAND */
224ae691e57SStefan Roese 
225ae691e57SStefan Roese /*
226ae691e57SStefan Roese  * Cache Configuration
227ae691e57SStefan Roese  */
228ae691e57SStefan Roese #define CONFIG_SYS_DCACHE_SIZE		16384
229ae691e57SStefan Roese #define CONFIG_SYS_ICACHE_SIZE		16384
230ae691e57SStefan Roese #define CONFIG_SYS_CACHELINE_SIZE	32
231ae691e57SStefan Roese 
232ae691e57SStefan Roese /*
233ae691e57SStefan Roese  * I2C/EEPROM
234ae691e57SStefan Roese  */
235ae691e57SStefan Roese #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
236ae691e57SStefan Roese #define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
237ae691e57SStefan Roese 
238ae691e57SStefan Roese #define CONFIG_SYS_I2C_SPEED		83000	/* 83 kHz is supposed to work	*/
239ae691e57SStefan Roese #define CONFIG_SYS_I2C_SLAVE		0x7f
240ae691e57SStefan Roese 
241ae691e57SStefan Roese /*
242ae691e57SStefan Roese  * Software (bit-bang) I2C driver configuration
243ae691e57SStefan Roese  */
244ae691e57SStefan Roese #define CONFIG_SYS_GPIO_I2C_SCL		11
245ae691e57SStefan Roese #define CONFIG_SYS_GPIO_I2C_SDA		10
246ae691e57SStefan Roese 
247ae691e57SStefan Roese #ifndef __ASSEMBLY__
248ae691e57SStefan Roese int vct_gpio_dir(int pin, int dir);
249ae691e57SStefan Roese void vct_gpio_set(int pin, int val);
250ae691e57SStefan Roese int vct_gpio_get(int pin);
251ae691e57SStefan Roese #endif
252ae691e57SStefan Roese 
253ae691e57SStefan Roese #define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
254ae691e57SStefan Roese #define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
255ae691e57SStefan Roese #define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
256ae691e57SStefan Roese #define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
257ae691e57SStefan Roese #define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
258ae691e57SStefan Roese #define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
259ae691e57SStefan Roese #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
260ae691e57SStefan Roese 
261ae691e57SStefan Roese #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
262ae691e57SStefan Roese /* CAT24WC32 */
263ae691e57SStefan Roese #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
264ae691e57SStefan Roese #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
265ae691e57SStefan Roese 					/* 32 byte page write mode using*/
266ae691e57SStefan Roese 					/* last 5 bits of the address	*/
267ae691e57SStefan Roese #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
268ae691e57SStefan Roese 
269ae691e57SStefan Roese #define CONFIG_BOOTCOMMAND	"run test3"
270ae691e57SStefan Roese #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
271ae691e57SStefan Roese 
272ae691e57SStefan Roese /*
273ae691e57SStefan Roese  * UBI configuration
274ae691e57SStefan Roese  */
275ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
276ae691e57SStefan Roese #define CONFIG_SYS_USE_UBI
277ae691e57SStefan Roese #define	CONFIG_CMD_JFFS2
278ae691e57SStefan Roese #define	CONFIG_CMD_UBI
279ae691e57SStefan Roese #define	CONFIG_RBTREE
280942556a9SStefan Roese #define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
281ae691e57SStefan Roese #define CONFIG_MTD_PARTITIONS
28268d7d651SStefan Roese #define CONFIG_CMD_MTDPARTS
283ae691e57SStefan Roese 
284ae691e57SStefan Roese #define MTDIDS_DEFAULT		"onenand0=onenand"
285ae691e57SStefan Roese #define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(u-boot),"	\
286ae691e57SStefan Roese 					"128k(env),"		\
287ae691e57SStefan Roese 					"20m(kernel),"		\
288ae691e57SStefan Roese 					"-(rootfs)"
289ae691e57SStefan Roese #endif
290ae691e57SStefan Roese 
291ae691e57SStefan Roese /*
292ae691e57SStefan Roese  * We need a small, stripped down image to fit into the first 128k OneNAND
293ae691e57SStefan Roese  * erase block (gzipped). This image only needs basic commands for FLASH
294ae691e57SStefan Roese  * (NOR/OneNAND) usage and Linux kernel booting.
295ae691e57SStefan Roese  */
296ae691e57SStefan Roese #if defined(CONFIG_VCT_SMALL_IMAGE)
297ae691e57SStefan Roese #undef CONFIG_CMD_ASKENV
29874de7aefSWolfgang Denk #undef CONFIG_CMD_BDI
29974de7aefSWolfgang Denk #undef CONFIG_CMD_BEDBUG
30074de7aefSWolfgang Denk #undef CONFIG_CMD_CACHE
30174de7aefSWolfgang Denk #undef CONFIG_CMD_CONSOLE
302ae691e57SStefan Roese #undef CONFIG_CMD_CRC32
303ae691e57SStefan Roese #undef CONFIG_CMD_DHCP
304ae691e57SStefan Roese #undef CONFIG_CMD_EEPROM
30574de7aefSWolfgang Denk #undef CONFIG_CMD_EEPROM
30674de7aefSWolfgang Denk #undef CONFIG_CMD_ELF
30774de7aefSWolfgang Denk #undef CONFIG_CMD_FAT
308ae691e57SStefan Roese #undef CONFIG_CMD_I2C
30974de7aefSWolfgang Denk #undef CONFIG_CMD_I2C
31074de7aefSWolfgang Denk #undef CONFIG_CMD_IRQ
31174de7aefSWolfgang Denk #undef CONFIG_CMD_ITEST
312ae691e57SStefan Roese #undef CONFIG_CMD_LOADB
313ae691e57SStefan Roese #undef CONFIG_CMD_LOADS
314ae691e57SStefan Roese #undef CONFIG_CMD_LOADY
31574de7aefSWolfgang Denk #undef CONFIG_CMD_MII
31674de7aefSWolfgang Denk #undef CONFIG_CMD_MISC
31774de7aefSWolfgang Denk #undef CONFIG_CMD_NET
31874de7aefSWolfgang Denk #undef CONFIG_CMD_PING
31974de7aefSWolfgang Denk #undef CONFIG_CMD_REGINFO
32074de7aefSWolfgang Denk #undef CONFIG_CMD_SNTP
32174de7aefSWolfgang Denk #undef CONFIG_CMD_SOURCE
32274de7aefSWolfgang Denk #undef CONFIG_CMD_STRINGS
32374de7aefSWolfgang Denk #undef CONFIG_CMD_TERMINAL
324ae691e57SStefan Roese #undef CONFIG_CMD_USB
325ae691e57SStefan Roese 
326736fead8SBen Warren #undef CONFIG_SMC911X
327ae691e57SStefan Roese #undef CONFIG_SOFT_I2C
32874de7aefSWolfgang Denk #undef CONFIG_SOURCE
329ae691e57SStefan Roese #undef CONFIG_SYS_LONGHELP
330ae691e57SStefan Roese #undef CONFIG_TIMESTAMP
331ae691e57SStefan Roese #endif /* CONFIG_VCT_SMALL_IMAGE */
332ae691e57SStefan Roese 
333ae691e57SStefan Roese #endif  /* __CONFIG_H */
334