1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* U-Boot - Common settings for UniPhier Family */ 10 11 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 12 #define __CONFIG_UNIPHIER_COMMON_H__ 13 14 #define CONFIG_ARMV7_PSCI_1_0 15 16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 17 18 /*----------------------------------------------------------------------- 19 * MMU and Cache Setting 20 *----------------------------------------------------------------------*/ 21 22 /* Comment out the following to enable L1 cache */ 23 /* #define CONFIG_SYS_ICACHE_OFF */ 24 /* #define CONFIG_SYS_DCACHE_OFF */ 25 26 #define CONFIG_DISPLAY_CPUINFO 27 #define CONFIG_DISPLAY_BOARDINFO 28 #define CONFIG_BOARD_LATE_INIT 29 30 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 31 32 #define CONFIG_TIMESTAMP 33 34 /* FLASH related */ 35 #define CONFIG_MTD_DEVICE 36 37 #define CONFIG_SMC911X_32_BIT 38 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 39 #define CONFIG_SMC911X_BASE 0 40 41 #ifdef CONFIG_MICRO_SUPPORT_CARD 42 #define CONFIG_SMC911X 43 #else 44 #define CONFIG_SYS_NO_FLASH 45 #endif 46 47 #define CONFIG_FLASH_CFI_DRIVER 48 #define CONFIG_SYS_FLASH_CFI 49 50 #define CONFIG_SYS_MAX_FLASH_SECT 256 51 #define CONFIG_SYS_MONITOR_BASE 0 52 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 53 #define CONFIG_SYS_FLASH_BASE 0 54 55 /* 56 * flash_toggle does not work for our support card. 57 * We need to use flash_status_poll. 58 */ 59 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 60 61 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 62 63 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 64 65 /* serial console configuration */ 66 #define CONFIG_BAUDRATE 115200 67 68 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 69 #define CONFIG_USE_ARCH_MEMSET 70 #define CONFIG_USE_ARCH_MEMCPY 71 #endif 72 73 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 74 75 #define CONFIG_CMDLINE_EDITING /* add command line history */ 76 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 77 /* Print Buffer Size */ 78 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 79 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 80 /* Boot Argument Buffer Size */ 81 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 82 83 #define CONFIG_CONS_INDEX 1 84 85 /* #define CONFIG_ENV_IS_NOWHERE */ 86 /* #define CONFIG_ENV_IS_IN_NAND */ 87 #define CONFIG_ENV_IS_IN_MMC 88 #define CONFIG_ENV_OFFSET 0x80000 89 #define CONFIG_ENV_SIZE 0x2000 90 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 91 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_SYS_MMC_ENV_PART 1 94 95 #ifdef CONFIG_ARM64 96 #define CPU_RELEASE_ADDR 0x80000000 97 #define COUNTER_FREQUENCY 50000000 98 #define CONFIG_GICV3 99 #define GICD_BASE 0x5fe00000 100 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 101 #define GICR_BASE 0x5fe40000 102 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 103 #define GICR_BASE 0x5fe80000 104 #endif 105 #else 106 /* Time clock 1MHz */ 107 #define CONFIG_SYS_TIMER_RATE 1000000 108 #endif 109 110 111 #define CONFIG_SYS_MAX_NAND_DEVICE 1 112 #define CONFIG_SYS_NAND_MAX_CHIPS 2 113 #define CONFIG_SYS_NAND_ONFI_DETECTION 114 115 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 116 117 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 118 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 119 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 120 #else 121 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 122 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 123 #endif 124 125 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 126 127 #define CONFIG_SYS_NAND_USE_FLASH_BBT 128 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 129 130 /* USB */ 131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 132 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 133 #define CONFIG_FAT_WRITE 134 #define CONFIG_DOS_PARTITION 135 136 /* SD/MMC */ 137 #define CONFIG_SUPPORT_EMMC_BOOT 138 #define CONFIG_GENERIC_MMC 139 140 /* memtest works on */ 141 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 142 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 143 144 /* 145 * Network Configuration 146 */ 147 #define CONFIG_SERVERIP 192.168.11.1 148 #define CONFIG_IPADDR 192.168.11.10 149 #define CONFIG_GATEWAYIP 192.168.11.1 150 #define CONFIG_NETMASK 255.255.255.0 151 152 #define CONFIG_LOADADDR 0x84000000 153 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 154 155 #define CONFIG_CMDLINE_EDITING /* add command line history */ 156 157 #define CONFIG_BOOTCOMMAND "run $bootmode" 158 159 #define CONFIG_ROOTPATH "/nfs/root/path" 160 #define CONFIG_NFSBOOTCOMMAND \ 161 "setenv bootargs $bootargs root=/dev/nfs rw " \ 162 "nfsroot=$serverip:$rootpath " \ 163 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 164 "run __nfsboot" 165 166 #ifdef CONFIG_FIT 167 #define CONFIG_BOOTFILE "fitImage" 168 #define LINUXBOOT_ENV_SETTINGS \ 169 "fit_addr=0x00100000\0" \ 170 "fit_addr_r=0x84100000\0" \ 171 "fit_size=0x00f00000\0" \ 172 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 173 "bootm $fit_addr\0" \ 174 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 175 "bootm $fit_addr_r\0" \ 176 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 177 "bootm $fit_addr_r\0" \ 178 "__nfsboot=run tftpboot\0" 179 #else 180 #ifdef CONFIG_ARM64 181 #define CONFIG_BOOTFILE "Image" 182 #define LINUXBOOT_CMD "booti" 183 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 184 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 185 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 186 #else 187 #define CONFIG_BOOTFILE "zImage" 188 #define LINUXBOOT_CMD "bootz" 189 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 190 #define KERNEL_SIZE "kernel_size=0x00800000\0" 191 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 192 #endif 193 #define LINUXBOOT_ENV_SETTINGS \ 194 "fdt_addr=0x00100000\0" \ 195 "fdt_addr_r=0x84100000\0" \ 196 "fdt_size=0x00008000\0" \ 197 "kernel_addr=0x00200000\0" \ 198 KERNEL_ADDR_R \ 199 KERNEL_SIZE \ 200 RAMDISK_ADDR \ 201 "ramdisk_addr_r=0x84a00000\0" \ 202 "ramdisk_size=0x00600000\0" \ 203 "ramdisk_file=rootfs.cpio.uboot\0" \ 204 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 205 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 206 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 207 "setexpr kernel_size $kernel_size / 4 &&" \ 208 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 209 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 210 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 211 "run boot_common\0" \ 212 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 213 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 214 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 215 "run boot_common\0" \ 216 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 217 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 218 "tftpboot $fdt_addr_r $fdt_file &&" \ 219 "run boot_common\0" \ 220 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 221 "tftpboot $fdt_addr_r $fdt_file &&" \ 222 "setenv ramdisk_addr_r - &&" \ 223 "run boot_common\0" 224 #endif 225 226 #define CONFIG_EXTRA_ENV_SETTINGS \ 227 "netdev=eth0\0" \ 228 "verify=n\0" \ 229 "nor_base=0x42000000\0" \ 230 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 231 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 232 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 233 "tftpboot $tmp_addr u-boot.bin\0" \ 234 "emmcupdate=mmcsetn &&" \ 235 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 236 "tftpboot u-boot-spl.bin &&" \ 237 "mmc write $loadaddr 0 80 &&" \ 238 "tftpboot u-boot.bin &&" \ 239 "mmc write $loadaddr 80 780\0" \ 240 "nandupdate=nand erase 0 0x00100000 &&" \ 241 "tftpboot u-boot-spl.bin &&" \ 242 "nand write $loadaddr 0 0x00010000 &&" \ 243 "tftpboot u-boot.bin &&" \ 244 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 245 LINUXBOOT_ENV_SETTINGS 246 247 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 248 249 #define CONFIG_SYS_SDRAM_BASE 0x80000000 250 #define CONFIG_NR_DRAM_BANKS 2 251 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 252 #define CONFIG_SYS_MEM_TOP_HIDE 64 253 254 #if defined(CONFIG_ARM64) 255 #define CONFIG_SPL_TEXT_BASE 0x30000000 256 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 257 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 258 defined(CONFIG_ARCH_UNIPHIER_SLD8) 259 #define CONFIG_SPL_TEXT_BASE 0x00040000 260 #else 261 #define CONFIG_SPL_TEXT_BASE 0x00100000 262 #endif 263 264 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 265 #define CONFIG_SPL_STACK (0x30014c00) 266 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 267 #define CONFIG_SPL_STACK (0x3001c000) 268 #else 269 #define CONFIG_SPL_STACK (0x00100000) 270 #endif 271 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 272 273 #define CONFIG_PANIC_HANG 274 275 #define CONFIG_SPL_FRAMEWORK 276 #ifdef CONFIG_ARM64 277 #define CONFIG_SPL_BOARD_LOAD_IMAGE 278 #endif 279 280 #define CONFIG_SPL_BOARD_INIT 281 282 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 283 284 /* subtract sizeof(struct image_header) */ 285 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 286 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 287 288 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 289 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 290 #define CONFIG_SPL_MAX_SIZE 0x10000 291 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 292 #define CONFIG_SPL_BSS_START_ADDR 0x30012000 293 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 294 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 295 #endif 296 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 297 298 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 299