1 /* 2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* U-boot - Common settings for UniPhier Family */ 8 9 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 10 #define __CONFIG_UNIPHIER_COMMON_H__ 11 12 #if defined(CONFIG_MACH_PH1_SLD3) 13 #define CONFIG_DDR_NUM_CH0 2 14 #define CONFIG_DDR_NUM_CH1 1 15 #define CONFIG_DDR_NUM_CH2 1 16 17 /* Physical start address of SDRAM */ 18 #define CONFIG_SDRAM0_BASE 0x80000000 19 #define CONFIG_SDRAM0_SIZE 0x20000000 20 #define CONFIG_SDRAM1_BASE 0xc0000000 21 #define CONFIG_SDRAM1_SIZE 0x20000000 22 #define CONFIG_SDRAM2_BASE 0xc0000000 23 #define CONFIG_SDRAM2_SIZE 0x10000000 24 #endif 25 26 #if defined(CONFIG_MACH_PH1_LD4) 27 #define CONFIG_DDR_NUM_CH0 1 28 #define CONFIG_DDR_NUM_CH1 1 29 30 /* Physical start address of SDRAM */ 31 #define CONFIG_SDRAM0_BASE 0x80000000 32 #define CONFIG_SDRAM0_SIZE 0x10000000 33 #define CONFIG_SDRAM1_BASE 0x90000000 34 #define CONFIG_SDRAM1_SIZE 0x10000000 35 #endif 36 37 #if defined(CONFIG_MACH_PH1_PRO4) 38 #define CONFIG_DDR_NUM_CH0 2 39 #define CONFIG_DDR_NUM_CH1 2 40 41 /* Physical start address of SDRAM */ 42 #define CONFIG_SDRAM0_BASE 0x80000000 43 #define CONFIG_SDRAM0_SIZE 0x20000000 44 #define CONFIG_SDRAM1_BASE 0xa0000000 45 #define CONFIG_SDRAM1_SIZE 0x20000000 46 #endif 47 48 #if defined(CONFIG_MACH_PH1_SLD8) 49 #define CONFIG_DDR_NUM_CH0 1 50 #define CONFIG_DDR_NUM_CH1 1 51 52 /* Physical start address of SDRAM */ 53 #define CONFIG_SDRAM0_BASE 0x80000000 54 #define CONFIG_SDRAM0_SIZE 0x10000000 55 #define CONFIG_SDRAM1_BASE 0x90000000 56 #define CONFIG_SDRAM1_SIZE 0x10000000 57 #endif 58 59 #define CONFIG_I2C_EEPROM 60 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 61 62 #ifdef CONFIG_SYS_NS16550_SERIAL 63 #define CONFIG_SYS_NS16550 64 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE 65 #define CONFIG_SYS_NS16550_CLK 12288000 66 #define CONFIG_SYS_NS16550_REG_SIZE -2 67 #endif 68 69 /* TODO: move to Kconfig and device tree */ 70 #if 0 71 #define CONFIG_SYS_NS16550_SERIAL 72 #endif 73 74 #define CONFIG_SMC911X 75 76 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 77 #define CONFIG_SMC911X_BASE 0 78 #define CONFIG_SMC911X_32_BIT 79 80 /*----------------------------------------------------------------------- 81 * MMU and Cache Setting 82 *----------------------------------------------------------------------*/ 83 84 /* Comment out the following to enable L1 cache */ 85 /* #define CONFIG_SYS_ICACHE_OFF */ 86 /* #define CONFIG_SYS_DCACHE_OFF */ 87 88 #define CONFIG_SYS_CACHELINE_SIZE 32 89 90 /* Comment out the following to enable L2 cache */ 91 #define CONFIG_UNIPHIER_L2CACHE_ON 92 93 #define CONFIG_DISPLAY_CPUINFO 94 #define CONFIG_DISPLAY_BOARDINFO 95 #define CONFIG_MISC_INIT_F 96 #define CONFIG_BOARD_EARLY_INIT_F 97 #define CONFIG_BOARD_EARLY_INIT_R 98 #define CONFIG_BOARD_LATE_INIT 99 100 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 101 102 #define CONFIG_TIMESTAMP 103 104 /* FLASH related */ 105 #define CONFIG_MTD_DEVICE 106 107 /* 108 * uncomment the following to disable FLASH related code. 109 */ 110 /* #define CONFIG_SYS_NO_FLASH */ 111 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_CFI 114 115 #define CONFIG_SYS_MAX_FLASH_SECT 256 116 #define CONFIG_SYS_MONITOR_BASE 0 117 #define CONFIG_SYS_FLASH_BASE 0 118 119 /* 120 * flash_toggle does not work for out supoort card. 121 * We need to use flash_status_poll. 122 */ 123 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 124 125 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 126 127 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 128 129 /* serial console configuration */ 130 #define CONFIG_BAUDRATE 115200 131 132 #define CONFIG_SYS_GENERIC_BOARD 133 134 #if !defined(CONFIG_SPL_BUILD) 135 #define CONFIG_USE_ARCH_MEMSET 136 #define CONFIG_USE_ARCH_MEMCPY 137 #endif 138 139 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 140 141 #define CONFIG_CMDLINE_EDITING /* add command line history */ 142 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 143 /* Print Buffer Size */ 144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 145 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 146 /* Boot Argument Buffer Size */ 147 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 148 149 #define CONFIG_CONS_INDEX 1 150 151 /* 152 * For NAND booting the environment is embedded in the U-Boot image. Please take 153 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. 154 */ 155 /* #define CONFIG_ENV_IS_IN_NAND */ 156 #define CONFIG_ENV_IS_NOWHERE 157 #define CONFIG_ENV_SIZE 0x2000 158 #define CONFIG_ENV_OFFSET 0x0 159 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 160 161 /* Time clock 1MHz */ 162 #define CONFIG_SYS_TIMER_RATE 1000000 163 164 /* 165 * By default, ARP timeout is 5 sec. 166 * The first ARP request does not seem to work. 167 * So we need to retry ARP request anyway. 168 * We want to shrink the interval until the second ARP request. 169 */ 170 #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ 171 172 #define CONFIG_SYS_MAX_NAND_DEVICE 1 173 #define CONFIG_SYS_NAND_MAX_CHIPS 2 174 #define CONFIG_SYS_NAND_ONFI_DETECTION 175 176 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 177 178 #ifdef CONFIG_MACH_PH1_SLD3 179 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 180 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 181 #else 182 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 183 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 184 #endif 185 186 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 187 188 #define CONFIG_SYS_NAND_USE_FLASH_BBT 189 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 190 191 /* USB */ 192 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 193 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 194 #define CONFIG_CMD_FAT 195 #define CONFIG_FAT_WRITE 196 #define CONFIG_DOS_PARTITION 197 198 /* memtest works on */ 199 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 200 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 201 202 #define CONFIG_BOOTDELAY 3 203 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 204 205 /* 206 * Network Configuration 207 */ 208 #define CONFIG_SERVERIP 192.168.11.1 209 #define CONFIG_IPADDR 192.168.11.10 210 #define CONFIG_GATEWAYIP 192.168.11.1 211 #define CONFIG_NETMASK 255.255.255.0 212 213 #define CONFIG_LOADADDR 0x84000000 214 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 215 216 #define CONFIG_CMDLINE_EDITING /* add command line history */ 217 218 #define CONFIG_BOOTCOMMAND "run $bootmode" 219 220 #define CONFIG_ROOTPATH "/nfs/root/path" 221 #define CONFIG_NFSBOOTCOMMAND \ 222 "setenv bootargs $bootargs root=/dev/nfs rw " \ 223 "nfsroot=$serverip:$rootpath " \ 224 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 225 "tftpboot; bootm;" 226 227 #define CONFIG_BOOTARGS " earlyprintk loglevel=8" 228 229 #ifdef CONFIG_FIT 230 #define CONFIG_BOOTFILE "fitImage" 231 #define LINUXBOOT_ENV_SETTINGS \ 232 "fit_addr=0x00100000\0" \ 233 "fit_addr_r=0x84100000\0" \ 234 "fit_size=0x00f00000\0" \ 235 "norboot=run add_default_bootargs &&" \ 236 "setexpr fit_addr $nor_base + $fit_addr &&" \ 237 "bootm $fit_addr\0" \ 238 "nandboot=run add_default_bootargs &&" \ 239 "nand read $fit_addr_r $fit_addr $fit_size &&" \ 240 "bootm $fit_addr_r\0" \ 241 "tftpboot=run add_default_bootargs &&" \ 242 "tftpboot $fit_addr_r $bootfile &&" \ 243 "bootm $fit_addr_r\0" 244 #else 245 #define CONFIG_BOOTFILE "uImage" 246 #define LINUXBOOT_ENV_SETTINGS \ 247 "fdt_addr=0x00100000\0" \ 248 "fdt_addr_r=0x84100000\0" \ 249 "fdt_size=0x00008000\0" \ 250 "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ 251 "kernel_addr=0x00200000\0" \ 252 "kernel_addr_r=0x84200000\0" \ 253 "kernel_size=0x00800000\0" \ 254 "ramdisk_addr=0x00a00000\0" \ 255 "ramdisk_addr_r=0x84a00000\0" \ 256 "ramdisk_size=0x00600000\0" \ 257 "ramdisk_file=rootfs.cpio.uboot\0" \ 258 "norboot=run add_default_bootargs &&" \ 259 "setexpr kernel_addr $nor_base + $kernel_addr &&" \ 260 "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ 261 "setexpr fdt_addr $nor_base + $fdt_addr &&" \ 262 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ 263 "nandboot=run add_default_bootargs &&" \ 264 "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 265 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 266 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 267 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 268 "tftpboot=run add_default_bootargs &&" \ 269 "tftpboot $kernel_addr_r $bootfile &&" \ 270 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 271 "tftpboot $fdt_addr_r $fdt_file &&" \ 272 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" 273 #endif 274 275 #define CONFIG_EXTRA_ENV_SETTINGS \ 276 "netdev=eth0\0" \ 277 "verify=n\0" \ 278 "norbase=0x42000000\0" \ 279 "nandupdate=nand erase 0 0x00100000 &&" \ 280 "tftpboot u-boot-spl-dtb.bin &&" \ 281 "nand write $loadaddr 0 0x00010000 &&" \ 282 "tftpboot u-boot-dtb.img &&" \ 283 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 284 "add_default_bootargs=setenv bootargs $bootargs" \ 285 " console=ttyS0,$baudrate\0" \ 286 LINUXBOOT_ENV_SETTINGS 287 288 /* Open Firmware flat tree */ 289 #define CONFIG_OF_LIBFDT 290 291 #define CONFIG_SYS_SDRAM_BASE 0x80000000 292 #define CONFIG_NR_DRAM_BANKS 2 293 294 #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ 295 defined(CONFIG_MACH_PH1_SLD8) 296 #define CONFIG_SPL_TEXT_BASE 0x00040000 297 #endif 298 #if defined(CONFIG_MACH_PH1_PRO4) 299 #define CONFIG_SPL_TEXT_BASE 0x00100000 300 #endif 301 302 #define CONFIG_SPL_STACK (0x0ff08000) 303 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 304 305 #define CONFIG_PANIC_HANG 306 307 #define CONFIG_SPL_FRAMEWORK 308 #define CONFIG_SPL_SERIAL_SUPPORT 309 #define CONFIG_SPL_NAND_SUPPORT 310 311 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ 312 #define CONFIG_SPL_LIBGENERIC_SUPPORT 313 314 #define CONFIG_SPL_BOARD_INIT 315 316 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 317 318 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 319 320 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 321