1*bd39050cSMarek Vasut /* 2*bd39050cSMarek Vasut * include/configs/ulcb.h 3*bd39050cSMarek Vasut * This file is ULCB board configuration. 4*bd39050cSMarek Vasut * 5*bd39050cSMarek Vasut * Copyright (C) 2017 Renesas Electronics Corporation 6*bd39050cSMarek Vasut * 7*bd39050cSMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 8*bd39050cSMarek Vasut */ 9*bd39050cSMarek Vasut 10*bd39050cSMarek Vasut #ifndef __ULCB_H 11*bd39050cSMarek Vasut #define __ULCB_H 12*bd39050cSMarek Vasut 13*bd39050cSMarek Vasut #undef DEBUG 14*bd39050cSMarek Vasut 15*bd39050cSMarek Vasut #define CONFIG_RCAR_BOARD_STRING "ULCB" 16*bd39050cSMarek Vasut 17*bd39050cSMarek Vasut #include "rcar-gen3-common.h" 18*bd39050cSMarek Vasut 19*bd39050cSMarek Vasut /* M3 ULCB has 2 banks, each with 1 GiB of RAM */ 20*bd39050cSMarek Vasut #if defined(CONFIG_R8A7796) 21*bd39050cSMarek Vasut #undef PHYS_SDRAM_1_SIZE 22*bd39050cSMarek Vasut #undef PHYS_SDRAM_2_SIZE 23*bd39050cSMarek Vasut #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) 24*bd39050cSMarek Vasut #define PHYS_SDRAM_2_SIZE 0x40000000u 25*bd39050cSMarek Vasut #endif 26*bd39050cSMarek Vasut 27*bd39050cSMarek Vasut /* SCIF */ 28*bd39050cSMarek Vasut #define CONFIG_SCIF_CONSOLE 29*bd39050cSMarek Vasut #define CONFIG_CONS_SCIF2 30*bd39050cSMarek Vasut #define CONFIG_CONS_INDEX 2 31*bd39050cSMarek Vasut #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ 32*bd39050cSMarek Vasut 33*bd39050cSMarek Vasut /* [A] Hyper Flash */ 34*bd39050cSMarek Vasut /* use to RPC(SPI Multi I/O Bus Controller) */ 35*bd39050cSMarek Vasut 36*bd39050cSMarek Vasut /* Ethernet RAVB */ 37*bd39050cSMarek Vasut #define CONFIG_NET_MULTI 38*bd39050cSMarek Vasut #define CONFIG_PHY_MICREL 39*bd39050cSMarek Vasut #define CONFIG_BITBANGMII 40*bd39050cSMarek Vasut #define CONFIG_BITBANGMII_MULTI 41*bd39050cSMarek Vasut 42*bd39050cSMarek Vasut /* Board Clock */ 43*bd39050cSMarek Vasut /* XTAL_CLK : 33.33MHz */ 44*bd39050cSMarek Vasut #define RCAR_XTAL_CLK 33333333u 45*bd39050cSMarek Vasut #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK 46*bd39050cSMarek Vasut /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ 47*bd39050cSMarek Vasut /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ 48*bd39050cSMarek Vasut #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 49*bd39050cSMarek Vasut #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) 50*bd39050cSMarek Vasut #define CONFIG_S3D2_CLK_FREQ (266666666u/2) 51*bd39050cSMarek Vasut #define CONFIG_S3D4_CLK_FREQ (266666666u/4) 52*bd39050cSMarek Vasut 53*bd39050cSMarek Vasut /* Generic Timer Definitions (use in assembler source) */ 54*bd39050cSMarek Vasut #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ 55*bd39050cSMarek Vasut 56*bd39050cSMarek Vasut /* Generic Interrupt Controller Definitions */ 57*bd39050cSMarek Vasut #define CONFIG_GICV2 58*bd39050cSMarek Vasut #define GICD_BASE 0xF1010000 59*bd39050cSMarek Vasut #define GICC_BASE 0xF1020000 60*bd39050cSMarek Vasut 61*bd39050cSMarek Vasut /* CPLD SPI */ 62*bd39050cSMarek Vasut #define CONFIG_CMD_SPI 63*bd39050cSMarek Vasut #define CONFIG_SOFT_SPI 64*bd39050cSMarek Vasut #define SPI_DELAY udelay(0) 65*bd39050cSMarek Vasut #define SPI_SDA(val) ulcb_softspi_sda(val) 66*bd39050cSMarek Vasut #define SPI_SCL(val) ulcb_softspi_scl(val) 67*bd39050cSMarek Vasut #define SPI_READ ulcb_softspi_read() 68*bd39050cSMarek Vasut #ifndef __ASSEMBLY__ 69*bd39050cSMarek Vasut void ulcb_softspi_sda(int); 70*bd39050cSMarek Vasut void ulcb_softspi_scl(int); 71*bd39050cSMarek Vasut unsigned char ulcb_softspi_read(void); 72*bd39050cSMarek Vasut #endif 73*bd39050cSMarek Vasut 74*bd39050cSMarek Vasut /* i2c */ 75*bd39050cSMarek Vasut #define CONFIG_SYS_I2C 76*bd39050cSMarek Vasut #define CONFIG_SYS_I2C_SH 77*bd39050cSMarek Vasut #define CONFIG_SYS_I2C_SLAVE 0x60 78*bd39050cSMarek Vasut #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 79*bd39050cSMarek Vasut #define CONFIG_SYS_I2C_SH_SPEED0 400000 80*bd39050cSMarek Vasut #define CONFIG_SH_I2C_DATA_HIGH 4 81*bd39050cSMarek Vasut #define CONFIG_SH_I2C_DATA_LOW 5 82*bd39050cSMarek Vasut #define CONFIG_SH_I2C_CLOCK 10000000 83*bd39050cSMarek Vasut 84*bd39050cSMarek Vasut #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 85*bd39050cSMarek Vasut 86*bd39050cSMarek Vasut /* USB */ 87*bd39050cSMarek Vasut #ifdef CONFIG_R8A7795 88*bd39050cSMarek Vasut #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 89*bd39050cSMarek Vasut #else 90*bd39050cSMarek Vasut #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 91*bd39050cSMarek Vasut #endif 92*bd39050cSMarek Vasut 93*bd39050cSMarek Vasut /* SDHI */ 94*bd39050cSMarek Vasut #define CONFIG_SH_SDHI_FREQ 200000000 95*bd39050cSMarek Vasut 96*bd39050cSMarek Vasut /* Environment in eMMC, at the end of 2nd "boot sector" */ 97*bd39050cSMarek Vasut #define CONFIG_ENV_IS_IN_MMC 98*bd39050cSMarek Vasut #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 99*bd39050cSMarek Vasut #define CONFIG_SYS_MMC_ENV_DEV 1 100*bd39050cSMarek Vasut #define CONFIG_SYS_MMC_ENV_PART 2 101*bd39050cSMarek Vasut 102*bd39050cSMarek Vasut /* Module stop status bits */ 103*bd39050cSMarek Vasut /* MFIS, SCIF1 */ 104*bd39050cSMarek Vasut #define CONFIG_SMSTP2_ENA 0x00002040 105*bd39050cSMarek Vasut /* SCIF2 */ 106*bd39050cSMarek Vasut #define CONFIG_SMSTP3_ENA 0x00000400 107*bd39050cSMarek Vasut /* INTC-AP, IRQC */ 108*bd39050cSMarek Vasut #define CONFIG_SMSTP4_ENA 0x00000180 109*bd39050cSMarek Vasut 110*bd39050cSMarek Vasut #endif /* __ULCB_H */ 111