13d657a05SEnric Balletbò i Serra /* 23d657a05SEnric Balletbò i Serra * (C) Copyright 2013 33d657a05SEnric Balletbò i Serra * Texas Instruments Incorporated. 43d657a05SEnric Balletbò i Serra * Sricharan R <r.sricharan@ti.com> 53d657a05SEnric Balletbò i Serra * 63d657a05SEnric Balletbò i Serra * Derived from OMAP4 done by: 73d657a05SEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 83d657a05SEnric Balletbò i Serra * 93d657a05SEnric Balletbò i Serra * TI OMAP5 AND DRA7XX common configuration settings 103d657a05SEnric Balletbò i Serra * 113d657a05SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 123d657a05SEnric Balletbò i Serra * 133d657a05SEnric Balletbò i Serra * For more details, please see the technical documents listed at 143d657a05SEnric Balletbò i Serra * http://www.ti.com/product/omap5432 153d657a05SEnric Balletbò i Serra */ 163d657a05SEnric Balletbò i Serra 173d657a05SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP5_COMMON_H 183d657a05SEnric Balletbò i Serra #define __CONFIG_TI_OMAP5_COMMON_H 193d657a05SEnric Balletbò i Serra 203d657a05SEnric Balletbò i Serra #define CONFIG_DISPLAY_CPUINFO 213d657a05SEnric Balletbò i Serra #define CONFIG_DISPLAY_BOARDINFO 223d657a05SEnric Balletbò i Serra #define CONFIG_ARCH_CPU_INIT 233d657a05SEnric Balletbò i Serra 245f603761SPraveen Rao /* Common ARM Erratas */ 255f603761SPraveen Rao #define CONFIG_ARM_ERRATA_798870 265f603761SPraveen Rao 273d657a05SEnric Balletbò i Serra #define CONFIG_SYS_CACHELINE_SIZE 64 283d657a05SEnric Balletbò i Serra 293d657a05SEnric Balletbò i Serra /* Use General purpose timer 1 */ 303d657a05SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 313d657a05SEnric Balletbò i Serra 323d657a05SEnric Balletbò i Serra /* 333d657a05SEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 343d657a05SEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 353d657a05SEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 363d657a05SEnric Balletbò i Serra */ 373d657a05SEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 383d657a05SEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 393d657a05SEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 403d657a05SEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 413d657a05SEnric Balletbò i Serra #endif 423d657a05SEnric Balletbò i Serra 433d657a05SEnric Balletbò i Serra #define CONFIG_PALMAS_POWER 443d657a05SEnric Balletbò i Serra 453d657a05SEnric Balletbò i Serra #include <asm/arch/cpu.h> 463d657a05SEnric Balletbò i Serra #include <asm/arch/omap.h> 473d657a05SEnric Balletbò i Serra 489a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 493d657a05SEnric Balletbò i Serra 503d657a05SEnric Balletbò i Serra /* 513d657a05SEnric Balletbò i Serra * Hardware drivers 523d657a05SEnric Balletbò i Serra */ 533d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550 54*c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK 48000000 5501e870b7STom Rini #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 563d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 573d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 5801e870b7STom Rini #else 59*c7b9686dSThomas Chou #define CONFIG_NS16550_SERIAL 6001e870b7STom Rini #endif 613d657a05SEnric Balletbò i Serra 623d657a05SEnric Balletbò i Serra /* 633d657a05SEnric Balletbò i Serra * Environment setup 643d657a05SEnric Balletbò i Serra */ 653d657a05SEnric Balletbò i Serra #ifndef PARTS_DEFAULT 663d657a05SEnric Balletbò i Serra #define PARTS_DEFAULT 673d657a05SEnric Balletbò i Serra #endif 683d657a05SEnric Balletbò i Serra 697a5a3e37SKishon Vijay Abraham I #ifndef DFUARGS 707a5a3e37SKishon Vijay Abraham I #define DFUARGS 717a5a3e37SKishon Vijay Abraham I #endif 727a5a3e37SKishon Vijay Abraham I 7308520bf5STom Rini #ifndef CONFIG_SPL_BUILD 744ec3f6e5SLokesh Vutla #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 753d657a05SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 76fb3ad9bdSTom Rini DEFAULT_LINUX_BOOT_ENV \ 7785d17be3SLokesh Vutla DEFAULT_MMC_TI_ARGS \ 783d657a05SEnric Balletbò i Serra "console=" CONSOLEDEV ",115200n8\0" \ 793d657a05SEnric Balletbò i Serra "fdtfile=undefined\0" \ 803d657a05SEnric Balletbò i Serra "bootpart=0:2\0" \ 813d657a05SEnric Balletbò i Serra "bootdir=/boot\0" \ 823d657a05SEnric Balletbò i Serra "bootfile=zImage\0" \ 833d657a05SEnric Balletbò i Serra "usbtty=cdc_acm\0" \ 843d657a05SEnric Balletbò i Serra "vram=16M\0" \ 853d657a05SEnric Balletbò i Serra "partitions=" PARTS_DEFAULT "\0" \ 863d657a05SEnric Balletbò i Serra "optargs=\0" \ 8716862604SLokesh Vutla "dofastboot=0\0" \ 883d657a05SEnric Balletbò i Serra "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 893d657a05SEnric Balletbò i Serra "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ 903d657a05SEnric Balletbò i Serra "source ${loadaddr}\0" \ 91fa58b102SCooper Jr., Franklin "bootenv=uEnv.txt\0" \ 92fa58b102SCooper Jr., Franklin "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ 933d657a05SEnric Balletbò i Serra "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ 943d657a05SEnric Balletbò i Serra "env import -t ${loadaddr} ${filesize}\0" \ 953d657a05SEnric Balletbò i Serra "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ 963d657a05SEnric Balletbò i Serra "mmcboot=mmc dev ${mmcdev}; " \ 973d657a05SEnric Balletbò i Serra "if mmc rescan; then " \ 983d657a05SEnric Balletbò i Serra "echo SD/MMC found on device ${mmcdev};" \ 993d657a05SEnric Balletbò i Serra "if run loadbootenv; then " \ 1003d657a05SEnric Balletbò i Serra "echo Loaded environment from ${bootenv};" \ 1013d657a05SEnric Balletbò i Serra "run importbootenv;" \ 1023d657a05SEnric Balletbò i Serra "fi;" \ 1033d657a05SEnric Balletbò i Serra "if test -n $uenvcmd; then " \ 1043d657a05SEnric Balletbò i Serra "echo Running uenvcmd ...;" \ 1053d657a05SEnric Balletbò i Serra "run uenvcmd;" \ 1063d657a05SEnric Balletbò i Serra "fi;" \ 1073d657a05SEnric Balletbò i Serra "if run loadimage; then " \ 1083d657a05SEnric Balletbò i Serra "run loadfdt; " \ 1093d657a05SEnric Balletbò i Serra "echo Booting from mmc${mmcdev} ...; " \ 11085d17be3SLokesh Vutla "run args_mmc; " \ 1113d657a05SEnric Balletbò i Serra "bootz ${loadaddr} - ${fdtaddr}; " \ 1123d657a05SEnric Balletbò i Serra "fi;" \ 1133d657a05SEnric Balletbò i Serra "fi;\0" \ 1143d657a05SEnric Balletbò i Serra "findfdt="\ 1153d657a05SEnric Balletbò i Serra "if test $board_name = omap5_uevm; then " \ 1163d657a05SEnric Balletbò i Serra "setenv fdtfile omap5-uevm.dtb; fi; " \ 1173d657a05SEnric Balletbò i Serra "if test $board_name = dra7xx; then " \ 1183d657a05SEnric Balletbò i Serra "setenv fdtfile dra7-evm.dtb; fi;" \ 1194ec3f6e5SLokesh Vutla "if test $board_name = dra72x; then " \ 1204ec3f6e5SLokesh Vutla "setenv fdtfile dra72-evm.dtb; fi;" \ 1211e4ad74bSFelipe Balbi "if test $board_name = beagle_x15; then " \ 1221e4ad74bSFelipe Balbi "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 1233d657a05SEnric Balletbò i Serra "if test $fdtfile = undefined; then " \ 1243d657a05SEnric Balletbò i Serra "echo WARNING: Could not determine device tree to use; fi; \0" \ 1253d657a05SEnric Balletbò i Serra "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ 1267a5a3e37SKishon Vijay Abraham I DFUARGS \ 1272320866bSCooper Jr., Franklin NETARGS \ 1283d657a05SEnric Balletbò i Serra 129ecd85579SDileep Katta 1303d657a05SEnric Balletbò i Serra #define CONFIG_BOOTCOMMAND \ 131ecd85579SDileep Katta "if test ${dofastboot} -eq 1; then " \ 132ecd85579SDileep Katta "echo Boot fastboot requested, resetting dofastboot ...;" \ 133ecd85579SDileep Katta "setenv dofastboot 0; saveenv;" \ 1348d2f0039SPaul Kocialkowski "echo Booting into fastboot ...; fastboot 0;" \ 135ecd85579SDileep Katta "fi;" \ 1363d657a05SEnric Balletbò i Serra "run findfdt; " \ 1373d657a05SEnric Balletbò i Serra "run mmcboot;" \ 1383d657a05SEnric Balletbò i Serra "setenv mmcdev 1; " \ 1393d657a05SEnric Balletbò i Serra "setenv bootpart 1:2; " \ 1403d657a05SEnric Balletbò i Serra "setenv mmcroot /dev/mmcblk0p2 rw; " \ 1413d657a05SEnric Balletbò i Serra "run mmcboot;" \ 142ecd85579SDileep Katta "" 14308520bf5STom Rini #endif 1443d657a05SEnric Balletbò i Serra 1453d657a05SEnric Balletbò i Serra 1463d657a05SEnric Balletbò i Serra /* 1473d657a05SEnric Balletbò i Serra * SPL related defines. The Public RAM memory map the ROM defines the 1483d657a05SEnric Balletbò i Serra * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 1493d657a05SEnric Balletbò i Serra * (dra7xx is larger, but we do not need to be larger at this time). We 1503d657a05SEnric Balletbò i Serra * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 1513d657a05SEnric Balletbò i Serra * print some information. 1523d657a05SEnric Balletbò i Serra */ 1533d657a05SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 1543d657a05SEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) 1553d657a05SEnric Balletbò i Serra #define CONFIG_SPL_DISPLAY_PRINT 1563d657a05SEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 157d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 158d3289aacSTom Rini (128 << 20)) 1593d657a05SEnric Balletbò i Serra 16070e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND 16170e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ 16270e71b61SEnric Balletbò i Serra #endif 16370e71b61SEnric Balletbò i Serra 164136b1013SMugunthan V N /* 165136b1013SMugunthan V N * Disable MMC DM for SPL build and can be re-enabled after adding 166136b1013SMugunthan V N * DM support in SPL 167136b1013SMugunthan V N */ 168136b1013SMugunthan V N #ifdef CONFIG_SPL_BUILD 169136b1013SMugunthan V N #undef CONFIG_DM_MMC 170136b1013SMugunthan V N #endif 171136b1013SMugunthan V N 1723d657a05SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 173