13d657a05SEnric Balletbò i Serra /* 23d657a05SEnric Balletbò i Serra * (C) Copyright 2013 33d657a05SEnric Balletbò i Serra * Texas Instruments Incorporated. 43d657a05SEnric Balletbò i Serra * Sricharan R <r.sricharan@ti.com> 53d657a05SEnric Balletbò i Serra * 63d657a05SEnric Balletbò i Serra * Derived from OMAP4 done by: 73d657a05SEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 83d657a05SEnric Balletbò i Serra * 93d657a05SEnric Balletbò i Serra * TI OMAP5 AND DRA7XX common configuration settings 103d657a05SEnric Balletbò i Serra * 113d657a05SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 123d657a05SEnric Balletbò i Serra * 133d657a05SEnric Balletbò i Serra * For more details, please see the technical documents listed at 143d657a05SEnric Balletbò i Serra * http://www.ti.com/product/omap5432 153d657a05SEnric Balletbò i Serra */ 163d657a05SEnric Balletbò i Serra 173d657a05SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP5_COMMON_H 183d657a05SEnric Balletbò i Serra #define __CONFIG_TI_OMAP5_COMMON_H 193d657a05SEnric Balletbò i Serra 203d657a05SEnric Balletbò i Serra /* Use General purpose timer 1 */ 213d657a05SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 223d657a05SEnric Balletbò i Serra 233d657a05SEnric Balletbò i Serra /* 243d657a05SEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 253d657a05SEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 263d657a05SEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 273d657a05SEnric Balletbò i Serra */ 283d657a05SEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 293d657a05SEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 303d657a05SEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 313d657a05SEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 323d657a05SEnric Balletbò i Serra #endif 333d657a05SEnric Balletbò i Serra 343d657a05SEnric Balletbò i Serra #define CONFIG_PALMAS_POWER 353d657a05SEnric Balletbò i Serra 363d657a05SEnric Balletbò i Serra #include <asm/arch/cpu.h> 373d657a05SEnric Balletbò i Serra #include <asm/arch/omap.h> 383d657a05SEnric Balletbò i Serra 399a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 403d657a05SEnric Balletbò i Serra 413d657a05SEnric Balletbò i Serra /* 423d657a05SEnric Balletbò i Serra * Hardware drivers 433d657a05SEnric Balletbò i Serra */ 44c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK 48000000 450a3f407aSLokesh Vutla #if !defined(CONFIG_DM_SERIAL) 463d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 473d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 4801e870b7STom Rini #endif 493d657a05SEnric Balletbò i Serra 503d657a05SEnric Balletbò i Serra /* 513d657a05SEnric Balletbò i Serra * Environment setup 523d657a05SEnric Balletbò i Serra */ 533d657a05SEnric Balletbò i Serra #ifndef PARTS_DEFAULT 543d657a05SEnric Balletbò i Serra #define PARTS_DEFAULT 553d657a05SEnric Balletbò i Serra #endif 563d657a05SEnric Balletbò i Serra 577a5a3e37SKishon Vijay Abraham I #ifndef DFUARGS 587a5a3e37SKishon Vijay Abraham I #define DFUARGS 597a5a3e37SKishon Vijay Abraham I #endif 607a5a3e37SKishon Vijay Abraham I 61*88fdfcd2SSekhar Nori #include <environment/ti/mmc.h> 62*88fdfcd2SSekhar Nori 634ec3f6e5SLokesh Vutla #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 643d657a05SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 65fb3ad9bdSTom Rini DEFAULT_LINUX_BOOT_ENV \ 6685d17be3SLokesh Vutla DEFAULT_MMC_TI_ARGS \ 671e93cc84SLokesh Vutla DEFAULT_FIT_TI_ARGS \ 683d657a05SEnric Balletbò i Serra "console=" CONSOLEDEV ",115200n8\0" \ 693d657a05SEnric Balletbò i Serra "fdtfile=undefined\0" \ 703d657a05SEnric Balletbò i Serra "bootpart=0:2\0" \ 713d657a05SEnric Balletbò i Serra "bootdir=/boot\0" \ 723d657a05SEnric Balletbò i Serra "bootfile=zImage\0" \ 733d657a05SEnric Balletbò i Serra "usbtty=cdc_acm\0" \ 743d657a05SEnric Balletbò i Serra "vram=16M\0" \ 753d657a05SEnric Balletbò i Serra "partitions=" PARTS_DEFAULT "\0" \ 763d657a05SEnric Balletbò i Serra "optargs=\0" \ 7716862604SLokesh Vutla "dofastboot=0\0" \ 783d657a05SEnric Balletbò i Serra "findfdt="\ 793d657a05SEnric Balletbò i Serra "if test $board_name = omap5_uevm; then " \ 803d657a05SEnric Balletbò i Serra "setenv fdtfile omap5-uevm.dtb; fi; " \ 813d657a05SEnric Balletbò i Serra "if test $board_name = dra7xx; then " \ 823d657a05SEnric Balletbò i Serra "setenv fdtfile dra7-evm.dtb; fi;" \ 83df6b506fSLokesh Vutla "if test $board_name = dra72x-revc; then " \ 84df6b506fSLokesh Vutla "setenv fdtfile dra72-evm-revc.dtb; fi;" \ 854ec3f6e5SLokesh Vutla "if test $board_name = dra72x; then " \ 864ec3f6e5SLokesh Vutla "setenv fdtfile dra72-evm.dtb; fi;" \ 87221fd361SNishanth Menon "if test $board_name = dra71x; then " \ 88221fd361SNishanth Menon "setenv fdtfile dra71-evm.dtb; fi;" \ 891e4ad74bSFelipe Balbi "if test $board_name = beagle_x15; then " \ 901e4ad74bSFelipe Balbi "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 91f7f9f6beSLokesh Vutla "if test $board_name = beagle_x15_revb1; then " \ 92f7f9f6beSLokesh Vutla "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \ 93cc5cdaadSLokesh Vutla "if test $board_name = am572x_idk; then " \ 94cc5cdaadSLokesh Vutla "setenv fdtfile am572x-idk.dtb; fi;" \ 95212f96f6SKipisz, Steven "if test $board_name = am57xx_evm; then " \ 96212f96f6SKipisz, Steven "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 97bf43ce6cSNishanth Menon "if test $board_name = am57xx_evm_reva3; then " \ 98bf43ce6cSNishanth Menon "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 994d8397c6SSteve Kipisz "if test $board_name = am571x_idk; then " \ 1004d8397c6SSteve Kipisz "setenv fdtfile am571x-idk.dtb; fi;" \ 1013d657a05SEnric Balletbò i Serra "if test $fdtfile = undefined; then " \ 1023d657a05SEnric Balletbò i Serra "echo WARNING: Could not determine device tree to use; fi; \0" \ 1037a5a3e37SKishon Vijay Abraham I DFUARGS \ 1042320866bSCooper Jr., Franklin NETARGS \ 1053d657a05SEnric Balletbò i Serra 1063d657a05SEnric Balletbò i Serra #define CONFIG_BOOTCOMMAND \ 107ecd85579SDileep Katta "if test ${dofastboot} -eq 1; then " \ 108ecd85579SDileep Katta "echo Boot fastboot requested, resetting dofastboot ...;" \ 109ecd85579SDileep Katta "setenv dofastboot 0; saveenv;" \ 110ada03c3cSSemen Protsenko "echo Booting into fastboot ...; " \ 111ada03c3cSSemen Protsenko "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \ 112ecd85579SDileep Katta "fi;" \ 1131e93cc84SLokesh Vutla "if test ${boot_fit} -eq 1; then " \ 1141e93cc84SLokesh Vutla "run update_to_fit;" \ 1151e93cc84SLokesh Vutla "fi;" \ 1163d657a05SEnric Balletbò i Serra "run findfdt; " \ 11718c534bbSLokesh Vutla "run envboot; " \ 1183d657a05SEnric Balletbò i Serra "run mmcboot;" \ 1193d657a05SEnric Balletbò i Serra "setenv mmcdev 1; " \ 1203d657a05SEnric Balletbò i Serra "setenv bootpart 1:2; " \ 1213d657a05SEnric Balletbò i Serra "setenv mmcroot /dev/mmcblk0p2 rw; " \ 1223d657a05SEnric Balletbò i Serra "run mmcboot;" \ 123ecd85579SDileep Katta "" 1243d657a05SEnric Balletbò i Serra 1253d657a05SEnric Balletbò i Serra /* 1263d657a05SEnric Balletbò i Serra * SPL related defines. The Public RAM memory map the ROM defines the 127b9b8403fSDaniel Allred * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. 128b9b8403fSDaniel Allred * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. 129b9b8403fSDaniel Allred * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 1303d657a05SEnric Balletbò i Serra * print some information. 1313d657a05SEnric Balletbò i Serra */ 132b9b8403fSDaniel Allred #ifdef CONFIG_TI_SECURE_DEVICE 133b9b8403fSDaniel Allred /* 134b9b8403fSDaniel Allred * For memory booting on HS parts, the first 4KB of the internal RAM is 135b9b8403fSDaniel Allred * reserved for secure world use and the flash loader image is 136b9b8403fSDaniel Allred * preceded by a secure certificate. The SPL will therefore run in internal 137b9b8403fSDaniel Allred * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). 138b9b8403fSDaniel Allred */ 139b9b8403fSDaniel Allred #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 140b9b8403fSDaniel Allred #define CONFIG_SPL_TEXT_BASE 0x40301350 14132d333f2SDaniel Allred /* If no specific start address is specified then the secure EMIF 14232d333f2SDaniel Allred * region will be placed at the end of the DDR space. In order to prevent 14332d333f2SDaniel Allred * the main u-boot relocation from clobbering that memory and causing a 14432d333f2SDaniel Allred * firewall violation, we tell u-boot that memory is protected RAM (PRAM) 14532d333f2SDaniel Allred */ 14632d333f2SDaniel Allred #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) 14732d333f2SDaniel Allred #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 14832d333f2SDaniel Allred #endif 149b9b8403fSDaniel Allred #else 150b9b8403fSDaniel Allred /* 151b9b8403fSDaniel Allred * For all booting on GP parts, the flash loader image is 152b9b8403fSDaniel Allred * downloaded into internal RAM at address 0x40300000. 153b9b8403fSDaniel Allred */ 1543d657a05SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 155b9b8403fSDaniel Allred #endif 156b9b8403fSDaniel Allred 157983e3700STom Rini #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 158d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 159d3289aacSTom Rini (128 << 20)) 1603d657a05SEnric Balletbò i Serra 16170e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND 16270e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ 16370e71b61SEnric Balletbò i Serra #endif 16470e71b61SEnric Balletbò i Serra 165136b1013SMugunthan V N #ifdef CONFIG_SPL_BUILD 16630a0cdb6SMugunthan V N #undef CONFIG_TIMER 167136b1013SMugunthan V N #endif 168136b1013SMugunthan V N 1693d657a05SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 170