xref: /rk3399_rockchip-uboot/include/configs/ti_omap5_common.h (revision 7a5a3e37bfc2caab0e8c191a4b3a06228dd1a558)
13d657a05SEnric Balletbò i Serra /*
23d657a05SEnric Balletbò i Serra  * (C) Copyright 2013
33d657a05SEnric Balletbò i Serra  * Texas Instruments Incorporated.
43d657a05SEnric Balletbò i Serra  * Sricharan R	  <r.sricharan@ti.com>
53d657a05SEnric Balletbò i Serra  *
63d657a05SEnric Balletbò i Serra  * Derived from OMAP4 done by:
73d657a05SEnric Balletbò i Serra  *	Aneesh V <aneesh@ti.com>
83d657a05SEnric Balletbò i Serra  *
93d657a05SEnric Balletbò i Serra  * TI OMAP5 AND DRA7XX common configuration settings
103d657a05SEnric Balletbò i Serra  *
113d657a05SEnric Balletbò i Serra  * SPDX-License-Identifier:	GPL-2.0+
123d657a05SEnric Balletbò i Serra  *
133d657a05SEnric Balletbò i Serra  * For more details, please see the technical documents listed at
143d657a05SEnric Balletbò i Serra  * http://www.ti.com/product/omap5432
153d657a05SEnric Balletbò i Serra  */
163d657a05SEnric Balletbò i Serra 
173d657a05SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP5_COMMON_H
183d657a05SEnric Balletbò i Serra #define __CONFIG_TI_OMAP5_COMMON_H
193d657a05SEnric Balletbò i Serra 
203d657a05SEnric Balletbò i Serra #define CONFIG_DISPLAY_CPUINFO
213d657a05SEnric Balletbò i Serra #define CONFIG_DISPLAY_BOARDINFO
223d657a05SEnric Balletbò i Serra #define CONFIG_ARCH_CPU_INIT
233d657a05SEnric Balletbò i Serra 
245f603761SPraveen Rao /* Common ARM Erratas */
255f603761SPraveen Rao #define CONFIG_ARM_ERRATA_798870
265f603761SPraveen Rao 
273d657a05SEnric Balletbò i Serra #define CONFIG_SYS_CACHELINE_SIZE	64
283d657a05SEnric Balletbò i Serra 
293d657a05SEnric Balletbò i Serra /* Use General purpose timer 1 */
303d657a05SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE		GPT2_BASE
313d657a05SEnric Balletbò i Serra 
323d657a05SEnric Balletbò i Serra /*
333d657a05SEnric Balletbò i Serra  * For the DDR timing information we can either dynamically determine
343d657a05SEnric Balletbò i Serra  * the timings to use or use pre-determined timings (based on using the
353d657a05SEnric Balletbò i Serra  * dynamic method.  Default to the static timing infomation.
363d657a05SEnric Balletbò i Serra  */
373d657a05SEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
383d657a05SEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
393d657a05SEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
403d657a05SEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
413d657a05SEnric Balletbò i Serra #endif
423d657a05SEnric Balletbò i Serra 
433d657a05SEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD
443d657a05SEnric Balletbò i Serra #define CONFIG_PALMAS_POWER
453d657a05SEnric Balletbò i Serra #endif
463d657a05SEnric Balletbò i Serra 
473d657a05SEnric Balletbò i Serra #include <asm/arch/cpu.h>
483d657a05SEnric Balletbò i Serra #include <asm/arch/omap.h>
493d657a05SEnric Balletbò i Serra 
503d657a05SEnric Balletbò i Serra #include <configs/ti_armv7_common.h>
513d657a05SEnric Balletbò i Serra 
523d657a05SEnric Balletbò i Serra /*
533d657a05SEnric Balletbò i Serra  * Hardware drivers
543d657a05SEnric Balletbò i Serra  */
553d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550
563d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL
573d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
583d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_CLK		48000000
593d657a05SEnric Balletbò i Serra 
603d657a05SEnric Balletbò i Serra /* Per-SoC commands */
613d657a05SEnric Balletbò i Serra #undef CONFIG_CMD_NET
623d657a05SEnric Balletbò i Serra #undef CONFIG_CMD_NFS
633d657a05SEnric Balletbò i Serra 
643d657a05SEnric Balletbò i Serra /*
653d657a05SEnric Balletbò i Serra  * Environment setup
663d657a05SEnric Balletbò i Serra  */
673d657a05SEnric Balletbò i Serra #ifndef PARTS_DEFAULT
683d657a05SEnric Balletbò i Serra #define PARTS_DEFAULT
693d657a05SEnric Balletbò i Serra #endif
703d657a05SEnric Balletbò i Serra 
71*7a5a3e37SKishon Vijay Abraham I #ifndef DFUARGS
72*7a5a3e37SKishon Vijay Abraham I #define DFUARGS
73*7a5a3e37SKishon Vijay Abraham I #endif
74*7a5a3e37SKishon Vijay Abraham I 
754ec3f6e5SLokesh Vutla #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
763d657a05SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \
77fb3ad9bdSTom Rini 	DEFAULT_LINUX_BOOT_ENV \
783d657a05SEnric Balletbò i Serra 	"console=" CONSOLEDEV ",115200n8\0" \
793d657a05SEnric Balletbò i Serra 	"fdtfile=undefined\0" \
803d657a05SEnric Balletbò i Serra 	"bootpart=0:2\0" \
813d657a05SEnric Balletbò i Serra 	"bootdir=/boot\0" \
823d657a05SEnric Balletbò i Serra 	"bootfile=zImage\0" \
833d657a05SEnric Balletbò i Serra 	"usbtty=cdc_acm\0" \
843d657a05SEnric Balletbò i Serra 	"vram=16M\0" \
853d657a05SEnric Balletbò i Serra 	"partitions=" PARTS_DEFAULT "\0" \
863d657a05SEnric Balletbò i Serra 	"optargs=\0" \
873d657a05SEnric Balletbò i Serra 	"mmcdev=0\0" \
88a70e157fSFranklin S Cooper Jr 	"mmcroot=/dev/mmcblk0p2 rw\0" \
893d657a05SEnric Balletbò i Serra 	"mmcrootfstype=ext4 rootwait\0" \
903d657a05SEnric Balletbò i Serra 	"mmcargs=setenv bootargs console=${console} " \
913d657a05SEnric Balletbò i Serra 		"${optargs} " \
923d657a05SEnric Balletbò i Serra 		"vram=${vram} " \
933d657a05SEnric Balletbò i Serra 		"root=${mmcroot} " \
943d657a05SEnric Balletbò i Serra 		"rootfstype=${mmcrootfstype}\0" \
95fa58b102SCooper Jr., Franklin 	"netargs=setenv bootargs console=${console} " \
96fa58b102SCooper Jr., Franklin 		"${optargs} " \
97fa58b102SCooper Jr., Franklin 		"root=/dev/nfs " \
98fa58b102SCooper Jr., Franklin 		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
99fa58b102SCooper Jr., Franklin 		"ip=dhcp\0" \
1003d657a05SEnric Balletbò i Serra 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
1013d657a05SEnric Balletbò i Serra 	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
1023d657a05SEnric Balletbò i Serra 		"source ${loadaddr}\0" \
103fa58b102SCooper Jr., Franklin 	"bootenv=uEnv.txt\0" \
104fa58b102SCooper Jr., Franklin 	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
1053d657a05SEnric Balletbò i Serra 	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
1063d657a05SEnric Balletbò i Serra 		"env import -t ${loadaddr} ${filesize}\0" \
1073d657a05SEnric Balletbò i Serra 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
1083d657a05SEnric Balletbò i Serra 	"mmcboot=mmc dev ${mmcdev}; " \
1093d657a05SEnric Balletbò i Serra 		"if mmc rescan; then " \
1103d657a05SEnric Balletbò i Serra 			"echo SD/MMC found on device ${mmcdev};" \
1113d657a05SEnric Balletbò i Serra 			"if run loadbootenv; then " \
1123d657a05SEnric Balletbò i Serra 				"echo Loaded environment from ${bootenv};" \
1133d657a05SEnric Balletbò i Serra 				"run importbootenv;" \
1143d657a05SEnric Balletbò i Serra 			"fi;" \
1153d657a05SEnric Balletbò i Serra 			"if test -n $uenvcmd; then " \
1163d657a05SEnric Balletbò i Serra 				"echo Running uenvcmd ...;" \
1173d657a05SEnric Balletbò i Serra 				"run uenvcmd;" \
1183d657a05SEnric Balletbò i Serra 			"fi;" \
1193d657a05SEnric Balletbò i Serra 			"if run loadimage; then " \
1203d657a05SEnric Balletbò i Serra 				"run loadfdt; " \
1213d657a05SEnric Balletbò i Serra 				"echo Booting from mmc${mmcdev} ...; " \
1223d657a05SEnric Balletbò i Serra 				"run mmcargs; " \
1233d657a05SEnric Balletbò i Serra 				"bootz ${loadaddr} - ${fdtaddr}; " \
1243d657a05SEnric Balletbò i Serra 			"fi;" \
1253d657a05SEnric Balletbò i Serra 		"fi;\0" \
126fa58b102SCooper Jr., Franklin 	"netboot=echo Booting from network ...; " \
127fa58b102SCooper Jr., Franklin 		"set env autoload no; " \
128fa58b102SCooper Jr., Franklin 		"dhcp; " \
129fa58b102SCooper Jr., Franklin 		"tftp ${loadaddr} ${bootfile}; " \
130fa58b102SCooper Jr., Franklin 		"tftp ${fdtaddr} ${fdtfile}; " \
131fa58b102SCooper Jr., Franklin 		"run netargs; " \
132fa58b102SCooper Jr., Franklin 		"bootz ${loadaddr} - ${fdtaddr}\0" \
1333d657a05SEnric Balletbò i Serra 	"findfdt="\
1343d657a05SEnric Balletbò i Serra 		"if test $board_name = omap5_uevm; then " \
1353d657a05SEnric Balletbò i Serra 			"setenv fdtfile omap5-uevm.dtb; fi; " \
1363d657a05SEnric Balletbò i Serra 		"if test $board_name = dra7xx; then " \
1373d657a05SEnric Balletbò i Serra 			"setenv fdtfile dra7-evm.dtb; fi;" \
1384ec3f6e5SLokesh Vutla 		"if test $board_name = dra72x; then " \
1394ec3f6e5SLokesh Vutla 			"setenv fdtfile dra72-evm.dtb; fi;" \
1401e4ad74bSFelipe Balbi 		"if test $board_name = beagle_x15; then " \
1411e4ad74bSFelipe Balbi 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
1423d657a05SEnric Balletbò i Serra 		"if test $fdtfile = undefined; then " \
1433d657a05SEnric Balletbò i Serra 			"echo WARNING: Could not determine device tree to use; fi; \0" \
1443d657a05SEnric Balletbò i Serra 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
145*7a5a3e37SKishon Vijay Abraham I 	DFUARGS \
1463d657a05SEnric Balletbò i Serra 
1473d657a05SEnric Balletbò i Serra #define CONFIG_BOOTCOMMAND \
1483d657a05SEnric Balletbò i Serra 	"run findfdt; " \
1493d657a05SEnric Balletbò i Serra 	"run mmcboot;" \
1503d657a05SEnric Balletbò i Serra 	"setenv mmcdev 1; " \
1513d657a05SEnric Balletbò i Serra 	"setenv bootpart 1:2; " \
1523d657a05SEnric Balletbò i Serra 	"setenv mmcroot /dev/mmcblk0p2 rw; " \
1533d657a05SEnric Balletbò i Serra 	"run mmcboot;" \
1543d657a05SEnric Balletbò i Serra 
1553d657a05SEnric Balletbò i Serra 
1563d657a05SEnric Balletbò i Serra /*
1573d657a05SEnric Balletbò i Serra  * SPL related defines.  The Public RAM memory map the ROM defines the
1583d657a05SEnric Balletbò i Serra  * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
1593d657a05SEnric Balletbò i Serra  * (dra7xx is larger, but we do not need to be larger at this time).  We
1603d657a05SEnric Balletbò i Serra  * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
1613d657a05SEnric Balletbò i Serra  * print some information.
1623d657a05SEnric Balletbò i Serra  */
1633d657a05SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE		0x40300000
1643d657a05SEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
1653d657a05SEnric Balletbò i Serra #define CONFIG_SPL_DISPLAY_PRINT
1663d657a05SEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
167d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
168d3289aacSTom Rini 					 (128 << 20))
1693d657a05SEnric Balletbò i Serra 
17070e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND
17170e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
17270e71b61SEnric Balletbò i Serra #endif
17370e71b61SEnric Balletbò i Serra 
1743d657a05SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP5_COMMON_H */
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