1*3d657a05SEnric Balletbò i Serra /* 2*3d657a05SEnric Balletbò i Serra * (C) Copyright 2013 3*3d657a05SEnric Balletbò i Serra * Texas Instruments Incorporated. 4*3d657a05SEnric Balletbò i Serra * Sricharan R <r.sricharan@ti.com> 5*3d657a05SEnric Balletbò i Serra * 6*3d657a05SEnric Balletbò i Serra * Derived from OMAP4 done by: 7*3d657a05SEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 8*3d657a05SEnric Balletbò i Serra * 9*3d657a05SEnric Balletbò i Serra * TI OMAP5 AND DRA7XX common configuration settings 10*3d657a05SEnric Balletbò i Serra * 11*3d657a05SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 12*3d657a05SEnric Balletbò i Serra * 13*3d657a05SEnric Balletbò i Serra * For more details, please see the technical documents listed at 14*3d657a05SEnric Balletbò i Serra * http://www.ti.com/product/omap5432 15*3d657a05SEnric Balletbò i Serra */ 16*3d657a05SEnric Balletbò i Serra 17*3d657a05SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP5_COMMON_H 18*3d657a05SEnric Balletbò i Serra #define __CONFIG_TI_OMAP5_COMMON_H 19*3d657a05SEnric Balletbò i Serra 20*3d657a05SEnric Balletbò i Serra #define CONFIG_OMAP54XX 21*3d657a05SEnric Balletbò i Serra #define CONFIG_DISPLAY_CPUINFO 22*3d657a05SEnric Balletbò i Serra #define CONFIG_DISPLAY_BOARDINFO 23*3d657a05SEnric Balletbò i Serra #define CONFIG_MISC_INIT_R 24*3d657a05SEnric Balletbò i Serra #define CONFIG_ARCH_CPU_INIT 25*3d657a05SEnric Balletbò i Serra 26*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_CACHELINE_SIZE 64 27*3d657a05SEnric Balletbò i Serra 28*3d657a05SEnric Balletbò i Serra /* Use General purpose timer 1 */ 29*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 30*3d657a05SEnric Balletbò i Serra 31*3d657a05SEnric Balletbò i Serra /* 32*3d657a05SEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 33*3d657a05SEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 34*3d657a05SEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 35*3d657a05SEnric Balletbò i Serra */ 36*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 37*3d657a05SEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 38*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 39*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 40*3d657a05SEnric Balletbò i Serra #endif 41*3d657a05SEnric Balletbò i Serra 42*3d657a05SEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD 43*3d657a05SEnric Balletbò i Serra #define CONFIG_PALMAS_POWER 44*3d657a05SEnric Balletbò i Serra #endif 45*3d657a05SEnric Balletbò i Serra 46*3d657a05SEnric Balletbò i Serra #include <asm/arch/cpu.h> 47*3d657a05SEnric Balletbò i Serra #include <asm/arch/omap.h> 48*3d657a05SEnric Balletbò i Serra 49*3d657a05SEnric Balletbò i Serra #define CONFIG_ENV_SIZE (128 << 10) 50*3d657a05SEnric Balletbò i Serra 51*3d657a05SEnric Balletbò i Serra #include <configs/ti_armv7_common.h> 52*3d657a05SEnric Balletbò i Serra 53*3d657a05SEnric Balletbò i Serra /* 54*3d657a05SEnric Balletbò i Serra * Hardware drivers 55*3d657a05SEnric Balletbò i Serra */ 56*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550 57*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 58*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 59*3d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_CLK 48000000 60*3d657a05SEnric Balletbò i Serra 61*3d657a05SEnric Balletbò i Serra /* Per-SoC commands */ 62*3d657a05SEnric Balletbò i Serra #undef CONFIG_CMD_NET 63*3d657a05SEnric Balletbò i Serra #undef CONFIG_CMD_NFS 64*3d657a05SEnric Balletbò i Serra 65*3d657a05SEnric Balletbò i Serra /* 66*3d657a05SEnric Balletbò i Serra * Environment setup 67*3d657a05SEnric Balletbò i Serra */ 68*3d657a05SEnric Balletbò i Serra #ifndef PARTS_DEFAULT 69*3d657a05SEnric Balletbò i Serra #define PARTS_DEFAULT 70*3d657a05SEnric Balletbò i Serra #endif 71*3d657a05SEnric Balletbò i Serra 72*3d657a05SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 73*3d657a05SEnric Balletbò i Serra "loadaddr=0x80200000\0" \ 74*3d657a05SEnric Balletbò i Serra "fdtaddr=0x80F80000\0" \ 75*3d657a05SEnric Balletbò i Serra "fdt_high=0xffffffff\0" \ 76*3d657a05SEnric Balletbò i Serra "rdaddr=0x81000000\0" \ 77*3d657a05SEnric Balletbò i Serra "console=" CONSOLEDEV ",115200n8\0" \ 78*3d657a05SEnric Balletbò i Serra "fdtfile=undefined\0" \ 79*3d657a05SEnric Balletbò i Serra "bootpart=0:2\0" \ 80*3d657a05SEnric Balletbò i Serra "bootdir=/boot\0" \ 81*3d657a05SEnric Balletbò i Serra "bootfile=zImage\0" \ 82*3d657a05SEnric Balletbò i Serra "usbtty=cdc_acm\0" \ 83*3d657a05SEnric Balletbò i Serra "vram=16M\0" \ 84*3d657a05SEnric Balletbò i Serra "partitions=" PARTS_DEFAULT "\0" \ 85*3d657a05SEnric Balletbò i Serra "optargs=\0" \ 86*3d657a05SEnric Balletbò i Serra "mmcdev=0\0" \ 87*3d657a05SEnric Balletbò i Serra "mmcroot=/dev/mmcblk1p2 rw\0" \ 88*3d657a05SEnric Balletbò i Serra "mmcrootfstype=ext4 rootwait\0" \ 89*3d657a05SEnric Balletbò i Serra "mmcargs=setenv bootargs console=${console} " \ 90*3d657a05SEnric Balletbò i Serra "${optargs} " \ 91*3d657a05SEnric Balletbò i Serra "vram=${vram} " \ 92*3d657a05SEnric Balletbò i Serra "root=${mmcroot} " \ 93*3d657a05SEnric Balletbò i Serra "rootfstype=${mmcrootfstype}\0" \ 94*3d657a05SEnric Balletbò i Serra "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 95*3d657a05SEnric Balletbò i Serra "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ 96*3d657a05SEnric Balletbò i Serra "source ${loadaddr}\0" \ 97*3d657a05SEnric Balletbò i Serra "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ 98*3d657a05SEnric Balletbò i Serra "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ 99*3d657a05SEnric Balletbò i Serra "env import -t ${loadaddr} ${filesize}\0" \ 100*3d657a05SEnric Balletbò i Serra "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ 101*3d657a05SEnric Balletbò i Serra "mmcboot=mmc dev ${mmcdev}; " \ 102*3d657a05SEnric Balletbò i Serra "if mmc rescan; then " \ 103*3d657a05SEnric Balletbò i Serra "echo SD/MMC found on device ${mmcdev};" \ 104*3d657a05SEnric Balletbò i Serra "if run loadbootenv; then " \ 105*3d657a05SEnric Balletbò i Serra "echo Loaded environment from ${bootenv};" \ 106*3d657a05SEnric Balletbò i Serra "run importbootenv;" \ 107*3d657a05SEnric Balletbò i Serra "fi;" \ 108*3d657a05SEnric Balletbò i Serra "if test -n $uenvcmd; then " \ 109*3d657a05SEnric Balletbò i Serra "echo Running uenvcmd ...;" \ 110*3d657a05SEnric Balletbò i Serra "run uenvcmd;" \ 111*3d657a05SEnric Balletbò i Serra "fi;" \ 112*3d657a05SEnric Balletbò i Serra "if run loadimage; then " \ 113*3d657a05SEnric Balletbò i Serra "run loadfdt; " \ 114*3d657a05SEnric Balletbò i Serra "echo Booting from mmc${mmcdev} ...; " \ 115*3d657a05SEnric Balletbò i Serra "run mmcargs; " \ 116*3d657a05SEnric Balletbò i Serra "bootz ${loadaddr} - ${fdtaddr}; " \ 117*3d657a05SEnric Balletbò i Serra "fi;" \ 118*3d657a05SEnric Balletbò i Serra "fi;\0" \ 119*3d657a05SEnric Balletbò i Serra "findfdt="\ 120*3d657a05SEnric Balletbò i Serra "if test $board_name = omap5_uevm; then " \ 121*3d657a05SEnric Balletbò i Serra "setenv fdtfile omap5-uevm.dtb; fi; " \ 122*3d657a05SEnric Balletbò i Serra "if test $board_name = dra7xx; then " \ 123*3d657a05SEnric Balletbò i Serra "setenv fdtfile dra7-evm.dtb; fi;" \ 124*3d657a05SEnric Balletbò i Serra "if test $fdtfile = undefined; then " \ 125*3d657a05SEnric Balletbò i Serra "echo WARNING: Could not determine device tree to use; fi; \0" \ 126*3d657a05SEnric Balletbò i Serra "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ 127*3d657a05SEnric Balletbò i Serra 128*3d657a05SEnric Balletbò i Serra #define CONFIG_BOOTCOMMAND \ 129*3d657a05SEnric Balletbò i Serra "run findfdt; " \ 130*3d657a05SEnric Balletbò i Serra "run mmcboot;" \ 131*3d657a05SEnric Balletbò i Serra "setenv mmcdev 1; " \ 132*3d657a05SEnric Balletbò i Serra "setenv bootpart 1:2; " \ 133*3d657a05SEnric Balletbò i Serra "setenv mmcroot /dev/mmcblk0p2 rw; " \ 134*3d657a05SEnric Balletbò i Serra "run mmcboot;" \ 135*3d657a05SEnric Balletbò i Serra 136*3d657a05SEnric Balletbò i Serra 137*3d657a05SEnric Balletbò i Serra /* 138*3d657a05SEnric Balletbò i Serra * SPL related defines. The Public RAM memory map the ROM defines the 139*3d657a05SEnric Balletbò i Serra * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 140*3d657a05SEnric Balletbò i Serra * (dra7xx is larger, but we do not need to be larger at this time). We 141*3d657a05SEnric Balletbò i Serra * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 142*3d657a05SEnric Balletbò i Serra * print some information. 143*3d657a05SEnric Balletbò i Serra */ 144*3d657a05SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 145*3d657a05SEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) 146*3d657a05SEnric Balletbò i Serra #define CONFIG_SPL_DISPLAY_PRINT 147*3d657a05SEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 148*3d657a05SEnric Balletbò i Serra 149*3d657a05SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 150