13d657a05SEnric Balletbò i Serra /* 23d657a05SEnric Balletbò i Serra * (C) Copyright 2013 33d657a05SEnric Balletbò i Serra * Texas Instruments Incorporated. 43d657a05SEnric Balletbò i Serra * Sricharan R <r.sricharan@ti.com> 53d657a05SEnric Balletbò i Serra * 63d657a05SEnric Balletbò i Serra * Derived from OMAP4 done by: 73d657a05SEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 83d657a05SEnric Balletbò i Serra * 93d657a05SEnric Balletbò i Serra * TI OMAP5 AND DRA7XX common configuration settings 103d657a05SEnric Balletbò i Serra * 113d657a05SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 123d657a05SEnric Balletbò i Serra * 133d657a05SEnric Balletbò i Serra * For more details, please see the technical documents listed at 143d657a05SEnric Balletbò i Serra * http://www.ti.com/product/omap5432 153d657a05SEnric Balletbò i Serra */ 163d657a05SEnric Balletbò i Serra 173d657a05SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP5_COMMON_H 183d657a05SEnric Balletbò i Serra #define __CONFIG_TI_OMAP5_COMMON_H 193d657a05SEnric Balletbò i Serra 205f603761SPraveen Rao /* Common ARM Erratas */ 215f603761SPraveen Rao #define CONFIG_ARM_ERRATA_798870 225f603761SPraveen Rao 233d657a05SEnric Balletbò i Serra /* Use General purpose timer 1 */ 243d657a05SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 253d657a05SEnric Balletbò i Serra 263d657a05SEnric Balletbò i Serra /* 273d657a05SEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 283d657a05SEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 293d657a05SEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 303d657a05SEnric Balletbò i Serra */ 313d657a05SEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 323d657a05SEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 333d657a05SEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 343d657a05SEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 353d657a05SEnric Balletbò i Serra #endif 363d657a05SEnric Balletbò i Serra 373d657a05SEnric Balletbò i Serra #define CONFIG_PALMAS_POWER 383d657a05SEnric Balletbò i Serra 393d657a05SEnric Balletbò i Serra #include <asm/arch/cpu.h> 403d657a05SEnric Balletbò i Serra #include <asm/arch/omap.h> 413d657a05SEnric Balletbò i Serra 429a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 433d657a05SEnric Balletbò i Serra 443d657a05SEnric Balletbò i Serra /* 453d657a05SEnric Balletbò i Serra * Hardware drivers 463d657a05SEnric Balletbò i Serra */ 47c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK 48000000 4801e870b7STom Rini #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 493d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 503d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 5101e870b7STom Rini #endif 523d657a05SEnric Balletbò i Serra 533d657a05SEnric Balletbò i Serra /* 543d657a05SEnric Balletbò i Serra * Environment setup 553d657a05SEnric Balletbò i Serra */ 563d657a05SEnric Balletbò i Serra #ifndef PARTS_DEFAULT 573d657a05SEnric Balletbò i Serra #define PARTS_DEFAULT 583d657a05SEnric Balletbò i Serra #endif 593d657a05SEnric Balletbò i Serra 607a5a3e37SKishon Vijay Abraham I #ifndef DFUARGS 617a5a3e37SKishon Vijay Abraham I #define DFUARGS 627a5a3e37SKishon Vijay Abraham I #endif 637a5a3e37SKishon Vijay Abraham I 644ec3f6e5SLokesh Vutla #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 653d657a05SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 66fb3ad9bdSTom Rini DEFAULT_LINUX_BOOT_ENV \ 6785d17be3SLokesh Vutla DEFAULT_MMC_TI_ARGS \ 68*1e93cc84SLokesh Vutla DEFAULT_FIT_TI_ARGS \ 693d657a05SEnric Balletbò i Serra "console=" CONSOLEDEV ",115200n8\0" \ 703d657a05SEnric Balletbò i Serra "fdtfile=undefined\0" \ 713d657a05SEnric Balletbò i Serra "bootpart=0:2\0" \ 723d657a05SEnric Balletbò i Serra "bootdir=/boot\0" \ 733d657a05SEnric Balletbò i Serra "bootfile=zImage\0" \ 743d657a05SEnric Balletbò i Serra "usbtty=cdc_acm\0" \ 753d657a05SEnric Balletbò i Serra "vram=16M\0" \ 763d657a05SEnric Balletbò i Serra "partitions=" PARTS_DEFAULT "\0" \ 773d657a05SEnric Balletbò i Serra "optargs=\0" \ 7816862604SLokesh Vutla "dofastboot=0\0" \ 793d657a05SEnric Balletbò i Serra "findfdt="\ 803d657a05SEnric Balletbò i Serra "if test $board_name = omap5_uevm; then " \ 813d657a05SEnric Balletbò i Serra "setenv fdtfile omap5-uevm.dtb; fi; " \ 823d657a05SEnric Balletbò i Serra "if test $board_name = dra7xx; then " \ 833d657a05SEnric Balletbò i Serra "setenv fdtfile dra7-evm.dtb; fi;" \ 84df6b506fSLokesh Vutla "if test $board_name = dra72x-revc; then " \ 85df6b506fSLokesh Vutla "setenv fdtfile dra72-evm-revc.dtb; fi;" \ 864ec3f6e5SLokesh Vutla "if test $board_name = dra72x; then " \ 874ec3f6e5SLokesh Vutla "setenv fdtfile dra72-evm.dtb; fi;" \ 881e4ad74bSFelipe Balbi "if test $board_name = beagle_x15; then " \ 891e4ad74bSFelipe Balbi "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 90cc5cdaadSLokesh Vutla "if test $board_name = am572x_idk; then " \ 91cc5cdaadSLokesh Vutla "setenv fdtfile am572x-idk.dtb; fi;" \ 92212f96f6SKipisz, Steven "if test $board_name = am57xx_evm; then " \ 93212f96f6SKipisz, Steven "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 943d657a05SEnric Balletbò i Serra "if test $fdtfile = undefined; then " \ 953d657a05SEnric Balletbò i Serra "echo WARNING: Could not determine device tree to use; fi; \0" \ 967a5a3e37SKishon Vijay Abraham I DFUARGS \ 972320866bSCooper Jr., Franklin NETARGS \ 983d657a05SEnric Balletbò i Serra 993d657a05SEnric Balletbò i Serra #define CONFIG_BOOTCOMMAND \ 100ecd85579SDileep Katta "if test ${dofastboot} -eq 1; then " \ 101ecd85579SDileep Katta "echo Boot fastboot requested, resetting dofastboot ...;" \ 102ecd85579SDileep Katta "setenv dofastboot 0; saveenv;" \ 103ada03c3cSSemen Protsenko "echo Booting into fastboot ...; " \ 104ada03c3cSSemen Protsenko "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \ 105ecd85579SDileep Katta "fi;" \ 106*1e93cc84SLokesh Vutla "if test ${boot_fit} -eq 1; then " \ 107*1e93cc84SLokesh Vutla "run update_to_fit;" \ 108*1e93cc84SLokesh Vutla "fi;" \ 1093d657a05SEnric Balletbò i Serra "run findfdt; " \ 11018c534bbSLokesh Vutla "run envboot; " \ 1113d657a05SEnric Balletbò i Serra "run mmcboot;" \ 1123d657a05SEnric Balletbò i Serra "setenv mmcdev 1; " \ 1133d657a05SEnric Balletbò i Serra "setenv bootpart 1:2; " \ 1143d657a05SEnric Balletbò i Serra "setenv mmcroot /dev/mmcblk0p2 rw; " \ 1153d657a05SEnric Balletbò i Serra "run mmcboot;" \ 116ecd85579SDileep Katta "" 1173d657a05SEnric Balletbò i Serra 1183d657a05SEnric Balletbò i Serra /* 1193d657a05SEnric Balletbò i Serra * SPL related defines. The Public RAM memory map the ROM defines the 120b9b8403fSDaniel Allred * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. 121b9b8403fSDaniel Allred * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. 122b9b8403fSDaniel Allred * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 1233d657a05SEnric Balletbò i Serra * print some information. 1243d657a05SEnric Balletbò i Serra */ 125b9b8403fSDaniel Allred #ifdef CONFIG_TI_SECURE_DEVICE 126b9b8403fSDaniel Allred /* 127b9b8403fSDaniel Allred * For memory booting on HS parts, the first 4KB of the internal RAM is 128b9b8403fSDaniel Allred * reserved for secure world use and the flash loader image is 129b9b8403fSDaniel Allred * preceded by a secure certificate. The SPL will therefore run in internal 130b9b8403fSDaniel Allred * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). 131b9b8403fSDaniel Allred */ 132b9b8403fSDaniel Allred #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 133b9b8403fSDaniel Allred #define CONFIG_SPL_TEXT_BASE 0x40301350 13432d333f2SDaniel Allred /* If no specific start address is specified then the secure EMIF 13532d333f2SDaniel Allred * region will be placed at the end of the DDR space. In order to prevent 13632d333f2SDaniel Allred * the main u-boot relocation from clobbering that memory and causing a 13732d333f2SDaniel Allred * firewall violation, we tell u-boot that memory is protected RAM (PRAM) 13832d333f2SDaniel Allred */ 13932d333f2SDaniel Allred #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) 14032d333f2SDaniel Allred #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 14132d333f2SDaniel Allred #endif 142b9b8403fSDaniel Allred #else 143b9b8403fSDaniel Allred /* 144b9b8403fSDaniel Allred * For all booting on GP parts, the flash loader image is 145b9b8403fSDaniel Allred * downloaded into internal RAM at address 0x40300000. 146b9b8403fSDaniel Allred */ 1473d657a05SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 148b9b8403fSDaniel Allred #endif 149b9b8403fSDaniel Allred 150983e3700STom Rini #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 151d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 152d3289aacSTom Rini (128 << 20)) 1533d657a05SEnric Balletbò i Serra 15470e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND 15570e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ 15670e71b61SEnric Balletbò i Serra #endif 15770e71b61SEnric Balletbò i Serra 158136b1013SMugunthan V N /* 159136b1013SMugunthan V N * Disable MMC DM for SPL build and can be re-enabled after adding 160136b1013SMugunthan V N * DM support in SPL 161136b1013SMugunthan V N */ 162136b1013SMugunthan V N #ifdef CONFIG_SPL_BUILD 163136b1013SMugunthan V N #undef CONFIG_DM_MMC 16430a0cdb6SMugunthan V N #undef CONFIG_TIMER 1653d12e804SMugunthan V N #undef CONFIG_DM_ETH 166136b1013SMugunthan V N #endif 167136b1013SMugunthan V N 1683d657a05SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 169