13d657a05SEnric Balletbò i Serra /* 23d657a05SEnric Balletbò i Serra * (C) Copyright 2013 33d657a05SEnric Balletbò i Serra * Texas Instruments Incorporated. 43d657a05SEnric Balletbò i Serra * Sricharan R <r.sricharan@ti.com> 53d657a05SEnric Balletbò i Serra * 63d657a05SEnric Balletbò i Serra * Derived from OMAP4 done by: 73d657a05SEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 83d657a05SEnric Balletbò i Serra * 93d657a05SEnric Balletbò i Serra * TI OMAP5 AND DRA7XX common configuration settings 103d657a05SEnric Balletbò i Serra * 113d657a05SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 123d657a05SEnric Balletbò i Serra * 133d657a05SEnric Balletbò i Serra * For more details, please see the technical documents listed at 143d657a05SEnric Balletbò i Serra * http://www.ti.com/product/omap5432 153d657a05SEnric Balletbò i Serra */ 163d657a05SEnric Balletbò i Serra 173d657a05SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP5_COMMON_H 183d657a05SEnric Balletbò i Serra #define __CONFIG_TI_OMAP5_COMMON_H 193d657a05SEnric Balletbò i Serra 203d657a05SEnric Balletbò i Serra /* Use General purpose timer 1 */ 213d657a05SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 223d657a05SEnric Balletbò i Serra 233d657a05SEnric Balletbò i Serra /* 243d657a05SEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 253d657a05SEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 263d657a05SEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 273d657a05SEnric Balletbò i Serra */ 283d657a05SEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 293d657a05SEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 303d657a05SEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 313d657a05SEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 323d657a05SEnric Balletbò i Serra #endif 333d657a05SEnric Balletbò i Serra 343d657a05SEnric Balletbò i Serra #define CONFIG_PALMAS_POWER 353d657a05SEnric Balletbò i Serra 363d657a05SEnric Balletbò i Serra #include <asm/arch/cpu.h> 373d657a05SEnric Balletbò i Serra #include <asm/arch/omap.h> 383d657a05SEnric Balletbò i Serra 399a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 403d657a05SEnric Balletbò i Serra 413d657a05SEnric Balletbò i Serra /* 423d657a05SEnric Balletbò i Serra * Hardware drivers 433d657a05SEnric Balletbò i Serra */ 44c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK 48000000 450a3f407aSLokesh Vutla #if !defined(CONFIG_DM_SERIAL) 463d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 473d657a05SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 4801e870b7STom Rini #endif 493d657a05SEnric Balletbò i Serra 503d657a05SEnric Balletbò i Serra /* 513d657a05SEnric Balletbò i Serra * Environment setup 523d657a05SEnric Balletbò i Serra */ 533d657a05SEnric Balletbò i Serra 547a5a3e37SKishon Vijay Abraham I #ifndef DFUARGS 557a5a3e37SKishon Vijay Abraham I #define DFUARGS 567a5a3e37SKishon Vijay Abraham I #endif 577a5a3e37SKishon Vijay Abraham I 58*4fd79ac9SSemen Protsenko #include <environment/ti/boot.h> 5988fdfcd2SSekhar Nori #include <environment/ti/mmc.h> 6088fdfcd2SSekhar Nori 614ec3f6e5SLokesh Vutla #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 623d657a05SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 63fb3ad9bdSTom Rini DEFAULT_LINUX_BOOT_ENV \ 6485d17be3SLokesh Vutla DEFAULT_MMC_TI_ARGS \ 651e93cc84SLokesh Vutla DEFAULT_FIT_TI_ARGS \ 66*4fd79ac9SSemen Protsenko DEFAULT_COMMON_BOOT_TI_ARGS \ 67*4fd79ac9SSemen Protsenko DEFAULT_FDT_TI_ARGS \ 687a5a3e37SKishon Vijay Abraham I DFUARGS \ 692320866bSCooper Jr., Franklin NETARGS \ 703d657a05SEnric Balletbò i Serra 713d657a05SEnric Balletbò i Serra /* 723d657a05SEnric Balletbò i Serra * SPL related defines. The Public RAM memory map the ROM defines the 73b9b8403fSDaniel Allred * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. 74b9b8403fSDaniel Allred * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. 75b9b8403fSDaniel Allred * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 763d657a05SEnric Balletbò i Serra * print some information. 773d657a05SEnric Balletbò i Serra */ 78b9b8403fSDaniel Allred #ifdef CONFIG_TI_SECURE_DEVICE 79b9b8403fSDaniel Allred /* 80b9b8403fSDaniel Allred * For memory booting on HS parts, the first 4KB of the internal RAM is 81b9b8403fSDaniel Allred * reserved for secure world use and the flash loader image is 82b9b8403fSDaniel Allred * preceded by a secure certificate. The SPL will therefore run in internal 83b9b8403fSDaniel Allred * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). 84b9b8403fSDaniel Allred */ 85b9b8403fSDaniel Allred #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 86b9b8403fSDaniel Allred #define CONFIG_SPL_TEXT_BASE 0x40301350 8732d333f2SDaniel Allred /* If no specific start address is specified then the secure EMIF 8832d333f2SDaniel Allred * region will be placed at the end of the DDR space. In order to prevent 8932d333f2SDaniel Allred * the main u-boot relocation from clobbering that memory and causing a 9032d333f2SDaniel Allred * firewall violation, we tell u-boot that memory is protected RAM (PRAM) 9132d333f2SDaniel Allred */ 9232d333f2SDaniel Allred #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) 9332d333f2SDaniel Allred #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 9432d333f2SDaniel Allred #endif 95b9b8403fSDaniel Allred #else 96b9b8403fSDaniel Allred /* 97b9b8403fSDaniel Allred * For all booting on GP parts, the flash loader image is 98b9b8403fSDaniel Allred * downloaded into internal RAM at address 0x40300000. 99b9b8403fSDaniel Allred */ 1003d657a05SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 101b9b8403fSDaniel Allred #endif 102b9b8403fSDaniel Allred 103d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 104d3289aacSTom Rini (128 << 20)) 1053d657a05SEnric Balletbò i Serra 106136b1013SMugunthan V N #ifdef CONFIG_SPL_BUILD 10730a0cdb6SMugunthan V N #undef CONFIG_TIMER 108136b1013SMugunthan V N #endif 109136b1013SMugunthan V N 1103d657a05SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 111