16c0a032aSEnric Balletbò i Serra /* 26c0a032aSEnric Balletbò i Serra * (C) Copyright 2010 36c0a032aSEnric Balletbò i Serra * Texas Instruments Incorporated. 46c0a032aSEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 56c0a032aSEnric Balletbò i Serra * Steve Sakoman <steve@sakoman.com> 66c0a032aSEnric Balletbò i Serra * 76c0a032aSEnric Balletbò i Serra * TI OMAP4 common configuration settings 86c0a032aSEnric Balletbò i Serra * 96c0a032aSEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 106c0a032aSEnric Balletbò i Serra */ 116c0a032aSEnric Balletbò i Serra 126c0a032aSEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP4_COMMON_H 136c0a032aSEnric Balletbò i Serra #define __CONFIG_TI_OMAP4_COMMON_H 146c0a032aSEnric Balletbò i Serra 156c0a032aSEnric Balletbò i Serra /* 166c0a032aSEnric Balletbò i Serra * High Level Configuration Options 176c0a032aSEnric Balletbò i Serra */ 186c0a032aSEnric Balletbò i Serra #define CONFIG_OMAP4430 1 /* which is in a 4430 */ 196c0a032aSEnric Balletbò i Serra #define CONFIG_MISC_INIT_R 206c0a032aSEnric Balletbò i Serra #define CONFIG_ARCH_CPU_INIT 216c0a032aSEnric Balletbò i Serra #define CONFIG_DISPLAY_CPUINFO 1 226c0a032aSEnric Balletbò i Serra #define CONFIG_DISPLAY_BOARDINFO 1 236c0a032aSEnric Balletbò i Serra 246c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_THUMB_BUILD 256c0a032aSEnric Balletbò i Serra 266c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_L2CACHE_OFF 276c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_L2_PL310 1 286c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_PL310_BASE 0x48242000 296c0a032aSEnric Balletbò i Serra #endif 306c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_CACHELINE_SIZE 32 316c0a032aSEnric Balletbò i Serra 326c0a032aSEnric Balletbò i Serra /* Get CPU defs */ 336c0a032aSEnric Balletbò i Serra #include <asm/arch/cpu.h> 346c0a032aSEnric Balletbò i Serra #include <asm/arch/omap.h> 356c0a032aSEnric Balletbò i Serra 366c0a032aSEnric Balletbò i Serra /* Use General purpose timer 1 */ 376c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 386c0a032aSEnric Balletbò i Serra 396c0a032aSEnric Balletbò i Serra /* 406c0a032aSEnric Balletbò i Serra * Total Size Environment - 128k 416c0a032aSEnric Balletbò i Serra */ 426c0a032aSEnric Balletbò i Serra #define CONFIG_ENV_SIZE (128 << 10) 436c0a032aSEnric Balletbò i Serra 446c0a032aSEnric Balletbò i Serra /* 456c0a032aSEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 466c0a032aSEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 476c0a032aSEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 486c0a032aSEnric Balletbò i Serra */ 496c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 506c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 516c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 526c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 536c0a032aSEnric Balletbò i Serra #endif 546c0a032aSEnric Balletbò i Serra 559a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 566c0a032aSEnric Balletbò i Serra 576c0a032aSEnric Balletbò i Serra /* 586c0a032aSEnric Balletbò i Serra * Hardware drivers 596c0a032aSEnric Balletbò i Serra */ 606c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550 61*c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK 48000000 6253ee6342STom Rini #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 636c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 646c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 656c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 UART3_BASE 6653ee6342STom Rini #else 67*c7b9686dSThomas Chou #define CONFIG_NS16550_SERIAL 6853ee6342STom Rini #endif 6953ee6342STom Rini #define CONFIG_CONS_INDEX 3 706c0a032aSEnric Balletbò i Serra 716c0a032aSEnric Balletbò i Serra /* TWL6030 */ 726c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD 736c0a032aSEnric Balletbò i Serra #define CONFIG_TWL6030_POWER 1 746c0a032aSEnric Balletbò i Serra #endif 756c0a032aSEnric Balletbò i Serra 766c0a032aSEnric Balletbò i Serra /* USB */ 7795de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_UDC 1 786c0a032aSEnric Balletbò i Serra #define CONFIG_USB_OMAP3 1 796c0a032aSEnric Balletbò i Serra 806c0a032aSEnric Balletbò i Serra /* USB device configuration */ 816c0a032aSEnric Balletbò i Serra #define CONFIG_USB_DEVICE 1 826c0a032aSEnric Balletbò i Serra #define CONFIG_USB_TTY 1 836c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 846c0a032aSEnric Balletbò i Serra 856c0a032aSEnric Balletbò i Serra /* 866c0a032aSEnric Balletbò i Serra * Environment setup 876c0a032aSEnric Balletbò i Serra */ 886c0a032aSEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 89fb3ad9bdSTom Rini DEFAULT_LINUX_BOOT_ENV \ 9085d17be3SLokesh Vutla DEFAULT_MMC_TI_ARGS \ 916c0a032aSEnric Balletbò i Serra "console=ttyO2,115200n8\0" \ 926c0a032aSEnric Balletbò i Serra "fdtfile=undefined\0" \ 936c0a032aSEnric Balletbò i Serra "bootpart=0:2\0" \ 946c0a032aSEnric Balletbò i Serra "bootdir=/boot\0" \ 956c0a032aSEnric Balletbò i Serra "bootfile=zImage\0" \ 966c0a032aSEnric Balletbò i Serra "usbtty=cdc_acm\0" \ 976c0a032aSEnric Balletbò i Serra "vram=16M\0" \ 9810226f29SGuillaume GARDET "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 996c0a032aSEnric Balletbò i Serra "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ 1006c0a032aSEnric Balletbò i Serra "source ${loadaddr}\0" \ 10110226f29SGuillaume GARDET "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ 1026c0a032aSEnric Balletbò i Serra "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ 1036c0a032aSEnric Balletbò i Serra "env import -t ${loadaddr} ${filesize}\0" \ 1046c0a032aSEnric Balletbò i Serra "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ 105ffe16911SAsh Charles "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ 1066c0a032aSEnric Balletbò i Serra "mmcboot=echo Booting from mmc${mmcdev} ...; " \ 10785d17be3SLokesh Vutla "run args_mmc; " \ 1086c0a032aSEnric Balletbò i Serra "bootz ${loadaddr} - ${fdtaddr}\0" \ 109ffe16911SAsh Charles "uimageboot=echo Booting from mmc${mmcdev} ...; " \ 11085d17be3SLokesh Vutla "run args_mmc; " \ 111ffe16911SAsh Charles "bootm ${loadaddr}\0" \ 1126c0a032aSEnric Balletbò i Serra "findfdt="\ 1136c0a032aSEnric Balletbò i Serra "if test $board_name = sdp4430; then " \ 1146c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-sdp.dtb; fi; " \ 1156c0a032aSEnric Balletbò i Serra "if test $board_name = panda; then " \ 1166c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-panda.dtb; fi;" \ 1176c0a032aSEnric Balletbò i Serra "if test $board_name = panda-a4; then " \ 1186c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-panda-a4.dtb; fi;" \ 1196c0a032aSEnric Balletbò i Serra "if test $board_name = panda-es; then " \ 1206c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-panda-es.dtb; fi;" \ 121ffe16911SAsh Charles "if test $board_name = duovero; then " \ 12299907176SAsh Charles "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ 1236c0a032aSEnric Balletbò i Serra "if test $fdtfile = undefined; then " \ 1246c0a032aSEnric Balletbò i Serra "echo WARNING: Could not determine device tree to use; fi; \0" \ 1256c0a032aSEnric Balletbò i Serra "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ 1266c0a032aSEnric Balletbò i Serra 1276c0a032aSEnric Balletbò i Serra #define CONFIG_BOOTCOMMAND \ 1286c0a032aSEnric Balletbò i Serra "run findfdt; " \ 1296c0a032aSEnric Balletbò i Serra "mmc dev ${mmcdev}; if mmc rescan; then " \ 1306c0a032aSEnric Balletbò i Serra "echo SD/MMC found on device ${mmcdev};" \ 1316c0a032aSEnric Balletbò i Serra "if run loadbootscript; then " \ 1326c0a032aSEnric Balletbò i Serra "run bootscript; " \ 1336c0a032aSEnric Balletbò i Serra "else " \ 1346c0a032aSEnric Balletbò i Serra "if run loadbootenv; then " \ 1356c0a032aSEnric Balletbò i Serra "run importbootenv; " \ 1366c0a032aSEnric Balletbò i Serra "fi;" \ 1376c0a032aSEnric Balletbò i Serra "if test -n ${uenvcmd}; then " \ 1386c0a032aSEnric Balletbò i Serra "echo Running uenvcmd ...;" \ 1396c0a032aSEnric Balletbò i Serra "run uenvcmd;" \ 1406c0a032aSEnric Balletbò i Serra "fi;" \ 1416c0a032aSEnric Balletbò i Serra "fi;" \ 1426c0a032aSEnric Balletbò i Serra "if run loadimage; then " \ 1436c0a032aSEnric Balletbò i Serra "run loadfdt;" \ 1446c0a032aSEnric Balletbò i Serra "run mmcboot; " \ 1456c0a032aSEnric Balletbò i Serra "fi; " \ 146ffe16911SAsh Charles "if run loaduimage; then " \ 147ffe16911SAsh Charles "run uimageboot;" \ 148ffe16911SAsh Charles "fi; " \ 1496c0a032aSEnric Balletbò i Serra "fi" 1506c0a032aSEnric Balletbò i Serra 1516c0a032aSEnric Balletbò i Serra /* 1526c0a032aSEnric Balletbò i Serra * Defines for SPL 1536c0a032aSEnric Balletbò i Serra * It is known that this will break HS devices. Since the current size of 1546c0a032aSEnric Balletbò i Serra * SPL is overlapped with public stack and breaking non HS devices to boot. 1556c0a032aSEnric Balletbò i Serra * So moving TEXT_BASE down to non-HS limit. 1566c0a032aSEnric Balletbò i Serra */ 1576c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 1586c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) 1596c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_DISPLAY_PRINT 1606c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 161d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 162d3289aacSTom Rini (128 << 20)) 1636c0a032aSEnric Balletbò i Serra 16470e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND 16570e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ 16670e71b61SEnric Balletbò i Serra #endif 16770e71b61SEnric Balletbò i Serra 1684f80d5baSNishanth Menon #ifdef CONFIG_SPL_BUILD 1694f80d5baSNishanth Menon /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ 1704f80d5baSNishanth Menon #undef CONFIG_SYS_I2C 1714f80d5baSNishanth Menon #undef CONFIG_SYS_I2C_OMAP24XX 17260c7c30aSPaul Kocialkowski #undef CONFIG_SPL_I2C_SUPPORT 1734f80d5baSNishanth Menon #endif 1744f80d5baSNishanth Menon 1756c0a032aSEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP4_COMMON_H */ 176